mirror of
https://git.wownero.com/wownero/RandomWOW.git
synced 2024-12-22 07:48:54 +00:00
e6ba0a1b7d
- fixed a crash in Instruction::print - new example program - added a design note about the number of x86 instruction per VM instruction
390 lines
11 KiB
C++
390 lines
11 KiB
C++
/*
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Copyright (c) 2018-2019, tevador <tevador@gmail.com>
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of the copyright holder nor the
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names of its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "instruction.hpp"
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#include "common.hpp"
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namespace randomx {
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void Instruction::print(std::ostream& os) const {
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os << names[opcode] << " ";
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auto handler = engine[opcode];
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(this->*handler)(os);
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}
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void Instruction::genAddressReg(std::ostream& os, int srcIndex) const {
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os << (getModMem() ? "L1" : "L2") << "[r" << srcIndex << std::showpos << (int32_t)getImm32() << std::noshowpos << "]";
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}
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void Instruction::genAddressRegDst(std::ostream& os, int dstIndex) const {
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if (getModCond() < StoreL3Condition)
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os << (getModMem() ? "L1" : "L2");
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else
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os << "L3";
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os << "[r" << dstIndex << std::showpos << (int32_t)getImm32() << std::noshowpos << "]";
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}
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void Instruction::genAddressImm(std::ostream& os) const {
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os << "L3" << "[" << (getImm32() & ScratchpadL3Mask) << "]";
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}
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void Instruction::h_IADD_RS(std::ostream& os) const {
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auto dstIndex = dst % RegistersCount;
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auto srcIndex = src % RegistersCount;
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os << "r" << dstIndex << ", r" << srcIndex;
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if(dstIndex == RegisterNeedsDisplacement) {
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os << ", " << (int32_t)getImm32();
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}
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os << ", SHFT " << getModShift() << std::endl;
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}
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void Instruction::h_IADD_M(std::ostream& os) const {
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auto dstIndex = dst % RegistersCount;
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auto srcIndex = src % RegistersCount;
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if (dstIndex != srcIndex) {
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os << "r" << dstIndex << ", ";
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genAddressReg(os, srcIndex);
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os << std::endl;
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}
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else {
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os << "r" << dstIndex << ", ";
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genAddressImm(os);
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os << std::endl;
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}
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}
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void Instruction::h_ISUB_R(std::ostream& os) const {
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auto dstIndex = dst % RegistersCount;
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auto srcIndex = src % RegistersCount;
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if (dstIndex != srcIndex) {
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os << "r" << dstIndex << ", r" << srcIndex << std::endl;
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}
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else {
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os << "r" << dstIndex << ", " << (int32_t)getImm32() << std::endl;
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}
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}
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void Instruction::h_ISUB_M(std::ostream& os) const {
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auto dstIndex = dst % RegistersCount;
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auto srcIndex = src % RegistersCount;
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if (dstIndex != srcIndex) {
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os << "r" << dstIndex << ", ";
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genAddressReg(os, srcIndex);
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os << std::endl;
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}
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else {
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os << "r" << dstIndex << ", ";
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genAddressImm(os);
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os << std::endl;
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}
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}
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void Instruction::h_IMUL_R(std::ostream& os) const {
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auto dstIndex = dst % RegistersCount;
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auto srcIndex = src % RegistersCount;
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if (dstIndex != srcIndex) {
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os << "r" << dstIndex << ", r" << srcIndex << std::endl;
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}
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else {
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os << "r" << dstIndex << ", " << (int32_t)getImm32() << std::endl;
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}
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}
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void Instruction::h_IMUL_M(std::ostream& os) const {
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auto dstIndex = dst % RegistersCount;
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auto srcIndex = src % RegistersCount;
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if (dstIndex != srcIndex) {
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os << "r" << dstIndex << ", ";
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genAddressReg(os, srcIndex);
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os << std::endl;
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}
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else {
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os << "r" << dstIndex << ", ";
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genAddressImm(os);
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os << std::endl;
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}
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}
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void Instruction::h_IMULH_R(std::ostream& os) const {
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auto dstIndex = dst % RegistersCount;
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auto srcIndex = src % RegistersCount;
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os << "r" << dstIndex << ", r" << srcIndex << std::endl;
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}
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void Instruction::h_IMULH_M(std::ostream& os) const {
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auto dstIndex = dst % RegistersCount;
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auto srcIndex = src % RegistersCount;
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if (dstIndex != srcIndex) {
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os << "r" << dstIndex << ", ";
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genAddressReg(os, srcIndex);
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os << std::endl;
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}
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else {
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os << "r" << dstIndex << ", ";
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genAddressImm(os);
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os << std::endl;
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}
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}
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void Instruction::h_ISMULH_R(std::ostream& os) const {
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auto dstIndex = dst % RegistersCount;
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auto srcIndex = src % RegistersCount;
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os << "r" << dstIndex << ", r" << srcIndex << std::endl;
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}
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void Instruction::h_ISMULH_M(std::ostream& os) const {
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auto dstIndex = dst % RegistersCount;
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auto srcIndex = src % RegistersCount;
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if (dstIndex != srcIndex) {
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os << "r" << dstIndex << ", ";
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genAddressReg(os, srcIndex);
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os << std::endl;
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}
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else {
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os << "r" << dstIndex << ", ";
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genAddressImm(os);
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os << std::endl;
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}
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}
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void Instruction::h_INEG_R(std::ostream& os) const {
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auto dstIndex = dst % RegistersCount;
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os << "r" << dstIndex << std::endl;
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}
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void Instruction::h_IXOR_R(std::ostream& os) const {
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auto dstIndex = dst % RegistersCount;
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auto srcIndex = src % RegistersCount;
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if (dstIndex != srcIndex) {
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os << "r" << dstIndex << ", r" << srcIndex << std::endl;
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}
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else {
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os << "r" << dstIndex << ", " << (int32_t)getImm32() << std::endl;
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}
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}
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void Instruction::h_IXOR_M(std::ostream& os) const {
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auto dstIndex = dst % RegistersCount;
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auto srcIndex = src % RegistersCount;
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if (dstIndex != srcIndex) {
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os << "r" << dstIndex << ", ";
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genAddressReg(os, srcIndex);
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os << std::endl;
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}
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else {
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os << "r" << dstIndex << ", ";
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genAddressImm(os);
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os << std::endl;
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}
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}
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void Instruction::h_IROR_R(std::ostream& os) const {
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auto dstIndex = dst % RegistersCount;
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auto srcIndex = src % RegistersCount;
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if (dstIndex != srcIndex) {
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os << "r" << dstIndex << ", r" << srcIndex << std::endl;
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}
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else {
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os << "r" << dstIndex << ", " << (getImm32() & 63) << std::endl;
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}
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}
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void Instruction::h_IROL_R(std::ostream& os) const {
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auto dstIndex = dst % RegistersCount;
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auto srcIndex = src % RegistersCount;
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if (dstIndex != srcIndex) {
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os << "r" << dstIndex << ", r" << srcIndex << std::endl;
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}
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else {
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os << "r" << dstIndex << ", " << (getImm32() & 63) << std::endl;
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}
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}
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void Instruction::h_IMUL_RCP(std::ostream& os) const {
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auto dstIndex = dst % RegistersCount;
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os << "r" << dstIndex << ", " << getImm32() << std::endl;
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}
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void Instruction::h_ISWAP_R(std::ostream& os) const {
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auto dstIndex = dst % RegistersCount;
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auto srcIndex = src % RegistersCount;
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os << "r" << dstIndex << ", r" << srcIndex << std::endl;
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}
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void Instruction::h_FSWAP_R(std::ostream& os) const {
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auto dstIndex = dst % RegistersCount;
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const char reg = (dstIndex >= RegisterCountFlt) ? 'e' : 'f';
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dstIndex %= RegisterCountFlt;
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os << reg << dstIndex << std::endl;
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}
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void Instruction::h_FADD_R(std::ostream& os) const {
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auto dstIndex = dst % RegisterCountFlt;
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auto srcIndex = src % RegisterCountFlt;
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os << "f" << dstIndex << ", a" << srcIndex << std::endl;
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}
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void Instruction::h_FADD_M(std::ostream& os) const {
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auto dstIndex = dst % RegisterCountFlt;
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auto srcIndex = src % RegistersCount;
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os << "f" << dstIndex << ", ";
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genAddressReg(os, srcIndex);
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os << std::endl;
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}
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void Instruction::h_FSUB_R(std::ostream& os) const {
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auto dstIndex = dst % RegisterCountFlt;
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auto srcIndex = src % RegisterCountFlt;
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os << "f" << dstIndex << ", a" << srcIndex << std::endl;
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}
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void Instruction::h_FSUB_M(std::ostream& os) const {
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auto dstIndex = dst % RegisterCountFlt;
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auto srcIndex = src % RegistersCount;
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os << "f" << dstIndex << ", ";
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genAddressReg(os, srcIndex);
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os << std::endl;
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}
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void Instruction::h_FSCAL_R(std::ostream& os) const {
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auto dstIndex = dst % RegisterCountFlt;
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os << "f" << dstIndex << std::endl;
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}
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void Instruction::h_FMUL_R(std::ostream& os) const {
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auto dstIndex = dst % RegisterCountFlt;
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auto srcIndex = src % RegisterCountFlt;
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os << "e" << dstIndex << ", a" << srcIndex << std::endl;
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}
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void Instruction::h_FDIV_M(std::ostream& os) const {
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auto dstIndex = dst % RegisterCountFlt;
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auto srcIndex = src % RegistersCount;
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os << "e" << dstIndex << ", ";
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genAddressReg(os, srcIndex);
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os << std::endl;
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}
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void Instruction::h_FSQRT_R(std::ostream& os) const {
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auto dstIndex = dst % RegisterCountFlt;
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os << "e" << dstIndex << std::endl;
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}
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void Instruction::h_CFROUND(std::ostream& os) const {
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auto srcIndex = src % RegistersCount;
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os << "r" << srcIndex << ", " << (getImm32() & 63) << std::endl;
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}
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void Instruction::h_CBRANCH(std::ostream& os) const {
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auto dstIndex = dst % RegistersCount;
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auto srcIndex = src % RegistersCount;
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os << "r" << dstIndex << ", " << (int32_t)getImm32() << ", COND " << (int)(getModCond()) << std::endl;
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}
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void Instruction::h_ISTORE(std::ostream& os) const {
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auto dstIndex = dst % RegistersCount;
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auto srcIndex = src % RegistersCount;
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genAddressRegDst(os, dstIndex);
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os << ", r" << srcIndex << std::endl;
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}
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void Instruction::h_NOP(std::ostream& os) const {
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os << std::endl;
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}
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#include "instruction_weights.hpp"
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#define INST_NAME(x) REPN(#x, WT(x))
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#define INST_HANDLE(x) REPN(&Instruction::h_##x, WT(x))
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const char* Instruction::names[256] = {
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INST_NAME(IADD_RS)
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INST_NAME(IADD_M)
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INST_NAME(ISUB_R)
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INST_NAME(ISUB_M)
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INST_NAME(IMUL_R)
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INST_NAME(IMUL_M)
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INST_NAME(IMULH_R)
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INST_NAME(IMULH_M)
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INST_NAME(ISMULH_R)
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INST_NAME(ISMULH_M)
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INST_NAME(IMUL_RCP)
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INST_NAME(INEG_R)
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INST_NAME(IXOR_R)
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INST_NAME(IXOR_M)
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INST_NAME(IROR_R)
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INST_NAME(IROL_R)
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INST_NAME(ISWAP_R)
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INST_NAME(FSWAP_R)
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INST_NAME(FADD_R)
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INST_NAME(FADD_M)
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INST_NAME(FSUB_R)
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INST_NAME(FSUB_M)
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INST_NAME(FSCAL_R)
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INST_NAME(FMUL_R)
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INST_NAME(FDIV_M)
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INST_NAME(FSQRT_R)
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INST_NAME(CBRANCH)
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INST_NAME(CFROUND)
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INST_NAME(ISTORE)
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INST_NAME(NOP)
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};
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InstructionFormatter Instruction::engine[256] = {
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INST_HANDLE(IADD_RS)
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INST_HANDLE(IADD_M)
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INST_HANDLE(ISUB_R)
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INST_HANDLE(ISUB_M)
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INST_HANDLE(IMUL_R)
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INST_HANDLE(IMUL_M)
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INST_HANDLE(IMULH_R)
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INST_HANDLE(IMULH_M)
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INST_HANDLE(ISMULH_R)
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INST_HANDLE(ISMULH_M)
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INST_HANDLE(IMUL_RCP)
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INST_HANDLE(INEG_R)
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INST_HANDLE(IXOR_R)
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INST_HANDLE(IXOR_M)
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INST_HANDLE(IROR_R)
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INST_HANDLE(IROL_R)
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INST_HANDLE(ISWAP_R)
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INST_HANDLE(FSWAP_R)
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INST_HANDLE(FADD_R)
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INST_HANDLE(FADD_M)
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INST_HANDLE(FSUB_R)
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INST_HANDLE(FSUB_M)
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INST_HANDLE(FSCAL_R)
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INST_HANDLE(FMUL_R)
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INST_HANDLE(FDIV_M)
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INST_HANDLE(FSQRT_R)
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INST_HANDLE(CBRANCH)
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INST_HANDLE(CFROUND)
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INST_HANDLE(ISTORE)
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INST_HANDLE(NOP)
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};
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} |