11 Commits

Author	SHA1	Message	Date
tevador	e6ba0a1b7d	Code generator fixups ... - fixed a crash in Instruction::print - new example program - added a design note about the number of x86 instruction per VM instruction	2019-06-23 23:10:29 +02:00
tevador	8a5ead5ce3	Use 'dst' as the CBRANCH condition register ... See issue #43	2019-05-21 08:37:36 +02:00
tevador	03dd2f397f	New sample program	2019-05-05 19:27:06 +02:00
tevador	9e5eac8645	Fixed a chance of CBRANCH looping ... Fixed CBRANCH jump probability being lower than expected	2019-05-03 14:02:40 +02:00
tevador	60d1fa2407	Updated sample program	2019-04-30 21:19:55 +02:00
tevador	3cf6a30076	Fixed biased condition register selection	2019-04-30 10:20:28 +02:00
tevador	ffebc37381	COND_R instruction reworked as CBRANCH ... instruction mod field bits reallocated	2019-04-29 23:38:23 +02:00
tevador	fd7186f873	Changed IADD_RS to use mod.mem	2019-04-27 23:52:26 +02:00
tevador	ff88a57a98	Fixed reading from the red zone	2019-04-26 23:32:10 +02:00
tevador	f66da3911e	Fixed some compilation issues ... Code cleanup	2019-04-26 11:07:47 +02:00
tevador	a8c7137873	Linux makefile ... Exception handling	2019-04-21 15:04:17 +02:00