12 Commits

Author	SHA1	Message	Date
tevador	b6d654291f	90 address transformations	2019-01-08 12:19:19 +01:00
tevador	2f6a599ff6	Inlined calls for memory read	2019-01-07 17:44:43 +01:00
tevador	619bee5418	Random dataset accesses - asm only ... Initial support for large pages	2019-01-04 19:44:15 +01:00
tevador	3caecc7646	Vector FPU instructions ... JitCompilerX86 - static code written in asm Updated ALU/FPU tests Updated instruction weights	2018-12-31 19:06:45 +01:00
tevador	a09bee8d60	js -> jz to enable macro-op fusion on Intel CPUs (~1% speed-up)	2018-12-28 14:18:41 +01:00
tevador	76b6b05cf2	Unconditional RET	2018-12-28 12:09:37 +01:00
tevador	740c40b218	8 branch conditions for CALL/RET	2018-12-21 22:41:35 +01:00
tevador	1db7dd6e8b	Renamed immediate constants	2018-12-20 18:36:09 +01:00
tevador	ed0bc906d6	JIT compiler for x86	2018-12-18 22:00:58 +01:00
tevador	4f276541d2	Modified x86 register allocation	2018-12-16 13:43:18 +01:00
tevador	6332831ec1	Implemented cache shift ... Fixed assembly code generator Fixed an error in the interpreter Updated specification: sign-extended immediates	2018-12-15 23:13:17 +01:00
tevador	cb0721056a	Assembly code generator for Windows 64-bit	2018-12-13 23:11:55 +01:00