mirror of
https://git.wownero.com/wownero/RandomWOW.git
synced 2024-12-22 07:48:54 +00:00
Renamed immediate constants
This commit is contained in:
tevador
parent
b9d2d853aa
commit
1db7dd6e8b
@ -43,4 +43,5 @@ The following people have contributed to the design of RandomX:
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RandomX uses some source code from the following 3rd party repositories:
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* Argon2d, Blake2b hashing functions: https://github.com/P-H-C/phc-winner-argon2
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* PCG32 random number generator: https://github.com/imneme/pcg-c-basic
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* Software AES implementation https://github.com/fireice-uk/xmr-stak
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* Software AES implementation https://github.com/fireice-uk/xmr-stak
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* t1ha2 hashing function: https://github.com/leo-yuriev/t1ha
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33
doc/isa.md
33
doc/isa.md
@ -1,10 +1,11 @@
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## RandomX instruction set
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RandomX uses a simple low-level language (instruction set), which was designed so that any random bitstring forms a valid program.
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Each RandomX instruction has a length of 128 bits. The encoding is following:
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*All flags are aligned to an 8-bit boundary for easier decoding.*
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@ -33,10 +34,10 @@ The first operand is read from memory. The location is determined by the `loc(a)
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Flag `reg(a)` encodes an integer register `r0`-`r7`. The read address is calculated as:
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```
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reg(a) = reg(a) XOR signExtend(addr0)
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addr(a) = reg(a)[W-1:0]
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reg(a) = reg(a) XOR signExtend(addr(a))
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read_addr = reg(a)[W-1:0]
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```
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`W` is the address width from the above table. For reading from the scratchpad, `addr(a)` is multiplied by 8 for 8-byte aligned access.
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`W` is the address width from the above table. For reading from the scratchpad, `read_addr` is multiplied by 8 for 8-byte aligned access.
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#### Operand B
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The second operand is loaded either from a register or from an immediate value encoded within the instruction. The `reg(b)` flag encodes an integer register (ALU operations) or a floating point register (FPU operations).
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@ -49,12 +50,12 @@ The second operand is loaded either from a register or from an immediate value e
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|011|register `reg(b)`|
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|100|register `reg(b)`|
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|101|register `reg(b)`|
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|110|`imm0` or `imm1`|
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|111|`imm0` or `imm1`|
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|110|`imm8` or `imm32`|
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|111|`imm8` or `imm32`|
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`imm0` is an 8-bit immediate value, which is used for shift and rotate ALU operations.
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`imm8` is an 8-bit immediate value, which is used for shift and rotate ALU operations.
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`imm1` is a 32-bit immediate value which is used for most operations. For operands larger than 32 bits, the value is sign-extended. For FPU instructions, the value is considered a signed 32-bit integer and then converted to a double precision floating point format.
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`imm32` is a 32-bit immediate value which is used for most operations. For operands larger than 32 bits, the value is sign-extended. For FPU instructions, the value is considered a signed 32-bit integer and then converted to a double precision floating point format.
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#### Operand C
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The third operand is the location where the result is stored.
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@ -72,18 +73,18 @@ The third operand is the location where the result is stored.
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The `reg(c)` flag encodes an integer register (ALU operations) or a floating point register (FPU operations). For writing to the scratchpad, an integer register is always used and the write address is calculated as:
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```
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addr(c) = 8 * (addr1 XOR reg(c)[31:0])[W-1:0]
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write_addr = 8 * (addr(c) XOR reg(c)[31:0])[W-1:0]
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```
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*CPUs are typically designed for a 2:1 load:store ratio, so each VM instruction performs on average 1 memory read and 0.5 write to memory.*
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#### imm0
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#### imm8
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An 8-bit immediate value that is used as the shift/rotate count by some ALU instructions and as the jump offset of the CALL instruction.
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#### addr0
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#### addr(a)
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A 32-bit address mask that is used to calculate the read address for the A operand. It's sign-extended to 64 bits.
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#### addr1
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A 32-bit address mask that is used to calculate the write address for the C operand. `addr1` is equal to `imm1`.
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#### addr\(c\)
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A 32-bit address mask that is used to calculate the write address for the C operand. `addr(c)` is equal to `imm32`.
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### ALU instructions
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@ -124,7 +125,7 @@ For the division instructions, the dividend is 64 bits long and the divisor 32 b
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*Division by zero can be handled without branching by a conditional move. Signed overflow happens only for the signed variant when the minimum negative value is divided by -1. This rare case must be handled in x86 (ARM produces the "correct" result).*
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##### Shift and rotate
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The shift/rotate instructions use just the bottom 6 bits of the `B` operand (`imm0` is used as the immediate value). All treat `A` as unsigned except SAR_64, which performs an arithmetic right shift by copying the sign bit.
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The shift/rotate instructions use just the bottom 6 bits of the `B` operand (`imm8` is used as the immediate value). All treat `A` as unsigned except SAR_64, which performs an arithmetic right shift by copying the sign bit.
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### FPU instructions
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@ -169,10 +170,10 @@ The following 2 control flow instructions are supported:
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|17|CALL|near procedure call|
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|15|RET|return from procedure|
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Both instructions are conditional in 75% of cases. The jump is taken only if `B <= imm1`. For the 25% of cases when `B` is equal to `imm1`, the jump is unconditional. In case the branch is not taken, both instructions become "arithmetic no-op" `C = A`.
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Both instructions are conditional in 75% of cases. The jump is taken only if `B <= imm32`. For the 25% of cases when `B` is equal to `imm32`, the jump is unconditional. In case the branch is not taken, both instructions become "arithmetic no-op" `C = A`.
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##### CALL
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Taken CALL instruction pushes the values `A` and `pc` (program counter) onto the stack and then performs a forward jump relative to the value of `pc`. The forward offset is equal to `16 * (imm0[6:0] + 1)`. Maximum jump distance is therefore 128 instructions forward (this means that at least 4 correctly spaced CALL instructions are needed to form a loop in the program).
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Taken CALL instruction pushes the values `A` and `pc` (program counter) onto the stack and then performs a forward jump relative to the value of `pc`. The forward offset is equal to `16 * (imm8[6:0] + 1)`. Maximum jump distance is therefore 128 instructions forward (this means that at least 4 correctly spaced CALL instructions are needed to form a loop in the program).
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##### RET
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The RET instruction behaves like "not taken" when the stack is empty. Taken RET instruction pops the return address `raddr` from the stack (it's the instruction following the previous CALL), then pops a return value `retval` from the stack and sets `C = A XOR retval`. Finally, the instruction jumps back to `raddr`.
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@ -55,7 +55,7 @@ namespace RandomX {
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}
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void AssemblyGeneratorX86::gena(Instruction& instr) {
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asmCode << "\txor " << regR[instr.rega % RegistersCount] << ", 0" << std::hex << instr.addr0 << "h" << std::dec << std::endl;
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asmCode << "\txor " << regR[instr.rega % RegistersCount] << ", 0" << std::hex << instr.addra << "h" << std::dec << std::endl;
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switch (instr.loca & 7)
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{
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case 0:
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@ -93,7 +93,7 @@ namespace RandomX {
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asmCode << "\t" << instrx86 << " rax, cl" << std::endl;
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return;
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default:
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asmCode << "\t" << instrx86 << " rax, " << (instr.imm0 & 63) << std::endl;;
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asmCode << "\t" << instrx86 << " rax, " << (instr.imm8 & 63) << std::endl;;
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return;
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}
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}
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@ -110,7 +110,7 @@ namespace RandomX {
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asmCode << regR[instr.regb % RegistersCount] << std::endl;
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return;
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default:
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asmCode << instr.imm1 << std::endl;;
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asmCode << instr.imm32 << std::endl;;
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return;
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}
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}
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@ -127,7 +127,7 @@ namespace RandomX {
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asmCode << regR32[instr.regb % RegistersCount] << std::endl;
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return;
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default:
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asmCode << instr.imm1 << std::endl;;
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asmCode << instr.imm32 << std::endl;;
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return;
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}
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}
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@ -147,7 +147,7 @@ namespace RandomX {
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return;
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default:
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convertible_t bimm;
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bimm.f64 = (double)instr.imm1;
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bimm.f64 = (double)instr.imm32;
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asmCode << "\tmov rax, " << bimm.i64 << std::endl;
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asmCode << "\tmovd xmm1, rax" << std::endl;
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asmCode << "\t" << instrx86 << " xmm0, xmm1" << std::endl;
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@ -161,7 +161,7 @@ namespace RandomX {
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case 0:
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asmCode << "\tmov rcx, rax" << std::endl;
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asmCode << "\tmov eax, " << regR32[instr.regc % RegistersCount] << std::endl;
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asmCode << "\txor eax, 0" << std::hex << instr.addr1 << "h" << std::dec << std::endl;
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asmCode << "\txor eax, 0" << std::hex << instr.addrc << "h" << std::dec << std::endl;
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asmCode << "\tand eax, " << (ScratchpadL2 - 1) << std::endl;
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asmCode << "\tmov qword ptr [rsi + rax * 8], rcx" << std::endl;
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if (trace) {
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@ -174,7 +174,7 @@ namespace RandomX {
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case 3:
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asmCode << "\tmov rcx, rax" << std::endl;
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asmCode << "\tmov eax, " << regR32[instr.regc % RegistersCount] << std::endl;
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asmCode << "\txor eax, 0" << std::hex << instr.addr1 << "h" << std::dec << std::endl;
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asmCode << "\txor eax, 0" << std::hex << instr.addrc << "h" << std::dec << std::endl;
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asmCode << "\tand eax, " << (ScratchpadL1 - 1) << std::endl;
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asmCode << "\tmov qword ptr [rsi + rax * 8], rcx" << std::endl;
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if (trace) {
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@ -195,7 +195,7 @@ namespace RandomX {
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{
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case 0:
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asmCode << "\tmov eax, " << regR32[instr.regc % RegistersCount] << std::endl;
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asmCode << "\txor eax, 0" << std::hex << instr.addr1 << "h" << std::dec << std::endl;
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asmCode << "\txor eax, 0" << std::hex << instr.addrc << "h" << std::dec << std::endl;
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asmCode << "\tand eax, " << (ScratchpadL2 - 1) << std::endl;
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asmCode << "\tmovd qword ptr [rsi + rax * 8], xmm0" << std::endl;
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break;
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@ -204,7 +204,7 @@ namespace RandomX {
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case 2:
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case 3:
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asmCode << "\tmov eax, " << regR32[instr.regc % RegistersCount] << std::endl;
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asmCode << "\txor eax, 0" << std::hex << instr.addr1 << "h" << std::dec << std::endl;
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asmCode << "\txor eax, 0" << std::hex << instr.addrc << "h" << std::dec << std::endl;
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asmCode << "\tand eax, " << (ScratchpadL1 - 1) << std::endl;
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asmCode << "\tmovd qword ptr [rsi + rax * 8], xmm0" << std::endl;
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break;
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@ -278,7 +278,7 @@ namespace RandomX {
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gena(instr);
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asmCode << "\tmovsxd rcx, eax" << std::endl;
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if ((instr.locb & 7) >= 6) {
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asmCode << "\tmov rax, " << instr.imm1 << std::endl;
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asmCode << "\tmov rax, " << instr.imm32 << std::endl;
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}
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else {
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asmCode << "\tmovsxd rax, " << regR32[instr.regb % RegistersCount] << std::endl;
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@ -299,11 +299,11 @@ namespace RandomX {
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void AssemblyGeneratorX86::h_DIV_64(Instruction& instr, int i) {
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gena(instr);
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if ((instr.locb & 7) >= 6) {
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if (instr.imm1 == 0) {
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if (instr.imm32 == 0) {
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asmCode << "\tmov ecx, 1" << std::endl;
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}
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else {
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asmCode << "\tmov ecx, " << instr.imm1 << std::endl;
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asmCode << "\tmov ecx, " << instr.imm32 << std::endl;
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}
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}
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else {
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@ -461,7 +461,7 @@ namespace RandomX {
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void AssemblyGeneratorX86::h_CALL(Instruction& instr, int i) {
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gena(instr);
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if ((instr.locb & 7) < 6) {
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asmCode << "\tcmp " << regR32[instr.regb % RegistersCount] << ", " << instr.imm1 << std::endl;
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asmCode << "\tcmp " << regR32[instr.regb % RegistersCount] << ", " << instr.imm32 << std::endl;
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asmCode << "\tjbe short taken_call_" << i << std::endl;
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gencr(instr);
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asmCode << "\tjmp rx_i_" << wrapInstr(i + 1) << std::endl;
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@ -471,7 +471,7 @@ namespace RandomX {
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asmCode << "\tmov qword ptr [rsi + rdi * 8 + 262144], rax" << std::endl;
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}
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asmCode << "\tpush rax" << std::endl;
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asmCode << "\tcall rx_i_" << wrapInstr(i + (instr.imm0 & 127) + 2) << std::endl;
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asmCode << "\tcall rx_i_" << wrapInstr(i + (instr.imm8 & 127) + 2) << std::endl;
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}
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void AssemblyGeneratorX86::h_RET(Instruction& instr, int i) {
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@ -479,7 +479,7 @@ namespace RandomX {
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asmCode << "\tcmp rsp, rbp" << std::endl;
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asmCode << "\tje short not_taken_ret_" << i << std::endl;
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if ((instr.locb & 7) < 6) {
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asmCode << "\tcmp " << regR32[instr.regb % RegistersCount] << ", " << instr.imm1 << std::endl;
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asmCode << "\tcmp " << regR32[instr.regb % RegistersCount] << ", " << instr.imm32 << std::endl;
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asmCode << "\tja short not_taken_ret_" << i << std::endl;
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}
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asmCode << "\txor rax, qword ptr [rsp + 8]" << std::endl;
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@ -25,10 +25,10 @@ namespace RandomX {
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os << " A: loc = " << std::dec << (loca & 7) << ", reg: " << (rega & 7) << std::endl;
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os << " B: loc = " << (locb & 7) << ", reg: " << (regb & 7) << std::endl;
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os << " C: loc = " << (locc & 7) << ", reg: " << (regc & 7) << std::endl;
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os << " addr0 = " << std::hex << addr0 << std::endl;
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os << " addr1 = " << addr1 << std::endl;
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os << " imm0 = " << std::dec << (int)imm0 << std::endl;
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os << " imm1 = " << imm1 << std::endl;
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os << " addra = " << std::hex << addra << std::endl;
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os << " addrc = " << addrc << std::endl;
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os << " imm8 = " << std::dec << (int)imm8 << std::endl;
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os << " imm32 = " << imm32 << std::endl;
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}
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#include "instructionWeights.hpp"
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@ -33,11 +33,11 @@ namespace RandomX {
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uint8_t regb;
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uint8_t locc;
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uint8_t regc;
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uint8_t imm0;
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int32_t addr0;
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uint8_t imm8;
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int32_t addra;
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union {
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uint32_t addr1;
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int32_t imm1;
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uint32_t addrc;
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int32_t imm32;
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};
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const char* getName() const {
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return names[opcode];
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@ -65,7 +65,7 @@ namespace RandomX {
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convertible_t InterpretedVirtualMachine::loada(Instruction& inst) {
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convertible_t& rega = reg.r[inst.rega % RegistersCount];
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rega.i64 ^= inst.addr0; //sign-extend addr0
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rega.i64 ^= inst.addra; //sign-extend addra
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addr_t addr = rega.u32;
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switch (inst.loca & 7)
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{
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@ -98,7 +98,7 @@ namespace RandomX {
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case 6:
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case 7:
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convertible_t temp;
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temp.i64 = inst.imm1; //sign-extend imm1
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temp.i64 = inst.imm32; //sign-extend imm32
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return temp;
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}
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}
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@ -116,7 +116,7 @@ namespace RandomX {
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case 6:
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case 7:
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convertible_t temp;
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temp.u64 = inst.imm0;
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temp.u64 = inst.imm8;
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return temp;
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}
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}
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@ -133,7 +133,7 @@ namespace RandomX {
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return reg.f[inst.regb % RegistersCount].f64;
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case 6:
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case 7:
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return (double)inst.imm1;
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return (double)inst.imm32;
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}
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}
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@ -142,13 +142,13 @@ namespace RandomX {
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switch (inst.locc & 7)
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{
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case 0:
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addr = reg.r[inst.regc % RegistersCount].u32 ^ inst.addr1;
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addr = reg.r[inst.regc % RegistersCount].u32 ^ inst.addrc;
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return scratchpad[addr % ScratchpadL2];
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case 1:
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case 2:
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case 3:
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addr = reg.r[inst.regc % RegistersCount].u32 ^ inst.addr1;
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addr = reg.r[inst.regc % RegistersCount].u32 ^ inst.addrc;
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return scratchpad[addr % ScratchpadL1];
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case 4:
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@ -164,13 +164,13 @@ namespace RandomX {
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switch (inst.locc & 7)
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{
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case 0:
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addr = reg.r[inst.regc % RegistersCount].u32 ^ inst.addr1;
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addr = reg.r[inst.regc % RegistersCount].u32 ^ inst.addrc;
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return scratchpad[addr % ScratchpadL2];
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case 1:
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case 2:
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case 3:
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addr = reg.r[inst.regc % RegistersCount].u32 ^ inst.addr1;
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addr = reg.r[inst.regc % RegistersCount].u32 ^ inst.addrc;
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return scratchpad[addr % ScratchpadL1];
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case 4:
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@ -272,10 +272,10 @@ namespace RandomX {
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convertible_t a = loada(inst);
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convertible_t b = loadbr1(inst);
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convertible_t& c = getcr(inst);
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if (b.u32 <= (uint32_t)inst.imm1) {
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if (b.u32 <= (uint32_t)inst.imm32) {
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stackPush(a);
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stackPush(pc);
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pc += (inst.imm0 & 127) + 1;
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pc += (inst.imm8 & 127) + 1;
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pc = pc % ProgramLength;
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if (trace) std::cout << std::hex << a.u64 << std::endl;
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}
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@ -289,7 +289,7 @@ namespace RandomX {
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convertible_t a = loada(inst);
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convertible_t b = loadbr1(inst);
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convertible_t& c = getcr(inst);
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if (stack.size() > 0 && b.u32 <= (uint32_t)inst.imm1) {
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if (stack.size() > 0 && b.u32 <= (uint32_t)inst.imm32) {
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auto raddr = stackPopAddress();
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auto retval = stackPopValue();
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c.u64 = a.u64 ^ retval.u64;
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@ -259,7 +259,7 @@ namespace RandomX {
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void JitCompilerX86::gena(Instruction& instr) {
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emit(uint16_t(0x8149)); //xor
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emitByte(0xf0 + (instr.rega % RegistersCount));
|
||||
emit(instr.addr0);
|
||||
emit(instr.addra);
|
||||
int32_t pc;
|
||||
switch (instr.loca & 7)
|
||||
{
|
||||
@ -301,7 +301,7 @@ namespace RandomX {
|
||||
else {
|
||||
emitByte(0x48); //REX.W
|
||||
emit(opcodeImm); //xxx rax, imm8
|
||||
emitByte((instr.imm0 & 63));
|
||||
emitByte((instr.imm8 & 63));
|
||||
}
|
||||
}
|
||||
|
||||
@ -312,7 +312,7 @@ namespace RandomX {
|
||||
}
|
||||
else {
|
||||
emit(opcodeImm); // xxx rax, imm32
|
||||
emit(instr.imm1);
|
||||
emit(instr.imm32);
|
||||
}
|
||||
}
|
||||
|
||||
@ -323,7 +323,7 @@ namespace RandomX {
|
||||
}
|
||||
else {
|
||||
emitByte(opcodeImm); // xxx eax, imm32
|
||||
emit(instr.imm1);
|
||||
emit(instr.imm32);
|
||||
}
|
||||
}
|
||||
|
||||
@ -343,7 +343,7 @@ namespace RandomX {
|
||||
}
|
||||
else {
|
||||
convertible_t bimm;
|
||||
bimm.f64 = (double)instr.imm1;
|
||||
bimm.f64 = (double)instr.imm32;
|
||||
emit(uint16_t(0xb848)); //movabs rax,imm64
|
||||
emit(bimm.i64);
|
||||
emitByte(0x66); //movq xmm1,rax
|
||||
@ -362,7 +362,7 @@ namespace RandomX {
|
||||
emitByte(0x8b); // mov
|
||||
emitByte(0xc0 + (instr.regc % RegistersCount)); //eax, regc
|
||||
emitByte(0x35); // xor eax
|
||||
emit(instr.addr1);
|
||||
emit(instr.addrc);
|
||||
emitByte(0x25); //and
|
||||
emit(ScratchpadL2 - 1); //whole scratchpad
|
||||
emit(0xc60c8948); // mov QWORD PTR [rsi+rax*8],rcx
|
||||
@ -375,7 +375,7 @@ namespace RandomX {
|
||||
emitByte(0x8b); // mov
|
||||
emitByte(0xc0 + (instr.regc % RegistersCount)); //eax, regc
|
||||
emitByte(0x35); // xor eax
|
||||
emit(instr.addr1);
|
||||
emit(instr.addrc);
|
||||
emitByte(0x25); //and
|
||||
emit(ScratchpadL1 - 1); //first 16 KiB of scratchpad
|
||||
emit(0xc60c8948); // mov QWORD PTR [rsi+rax*8],rcx
|
||||
@ -396,7 +396,7 @@ namespace RandomX {
|
||||
emit(uint16_t(0x8b41)); //mov
|
||||
emitByte(0xc0 + regc); //eax, regc
|
||||
emitByte(0x35); // xor eax
|
||||
emit(instr.addr1);
|
||||
emit(instr.addrc);
|
||||
emitByte(0x25); //and
|
||||
emit(ScratchpadL2 - 1); //whole scratchpad
|
||||
emit(uint16_t(0x4866)); //prefix
|
||||
@ -409,7 +409,7 @@ namespace RandomX {
|
||||
emit(uint16_t(0x8b41)); //mov
|
||||
emitByte(0xc0 + regc); //eax, regc
|
||||
emitByte(0x35); // xor eax
|
||||
emit(instr.addr1);
|
||||
emit(instr.addrc);
|
||||
emitByte(0x25); //and
|
||||
emit(ScratchpadL1 - 1); //first 16 KiB of scratchpad
|
||||
emit(uint16_t(0x4866)); //prefix
|
||||
@ -456,7 +456,7 @@ namespace RandomX {
|
||||
else {
|
||||
emitByte(0x48); //REX
|
||||
emit(uint16_t(0xc069)); // imul rax, rax, imm32
|
||||
emit(instr.imm1);
|
||||
emit(instr.imm32);
|
||||
}
|
||||
gencr(instr);
|
||||
}
|
||||
@ -469,7 +469,7 @@ namespace RandomX {
|
||||
else {
|
||||
emitByte(0x48);
|
||||
emit(uint16_t(0xc1c7)); // mov rcx, imm32
|
||||
emit(instr.imm1);
|
||||
emit(instr.imm32);
|
||||
}
|
||||
emitByte(0x48);
|
||||
emit(uint16_t(0xe1f7)); // mul rcx
|
||||
@ -486,7 +486,7 @@ namespace RandomX {
|
||||
}
|
||||
else {
|
||||
emitByte(0xb8); // mov eax, imm32
|
||||
emit(instr.imm1);
|
||||
emit(instr.imm32);
|
||||
}
|
||||
emit(0xc1af0f48); //imul rax,rcx
|
||||
gencr(instr);
|
||||
@ -502,7 +502,7 @@ namespace RandomX {
|
||||
else {
|
||||
emitByte(0x48);
|
||||
emit(uint16_t(0xc0c7)); // mov rax, imm32
|
||||
emit(instr.imm1);
|
||||
emit(instr.imm32);
|
||||
}
|
||||
emit(0xc1af0f48); //imul rax,rcx
|
||||
gencr(instr);
|
||||
@ -516,7 +516,7 @@ namespace RandomX {
|
||||
else {
|
||||
emitByte(0x48);
|
||||
emit(uint16_t(0xc1c7)); // mov rcx, imm32
|
||||
emit(instr.imm1);
|
||||
emit(instr.imm32);
|
||||
}
|
||||
emitByte(0x48);
|
||||
emit(uint16_t(0xe9f7)); // imul rcx
|
||||
@ -536,7 +536,7 @@ namespace RandomX {
|
||||
}
|
||||
else {
|
||||
emitByte(0xb9); //mov ecx, imm32
|
||||
emit(instr.imm1 != 0 ? instr.imm1 : 1);
|
||||
emit(instr.imm32 != 0 ? instr.imm32 : 1);
|
||||
}
|
||||
emit(0xf748d233); //xor edx,edx; div rcx
|
||||
emitByte(0xf1);
|
||||
@ -550,7 +550,7 @@ namespace RandomX {
|
||||
}
|
||||
else {
|
||||
emitByte(0xba); // xxx edx, imm32
|
||||
emit(instr.imm1);
|
||||
emit(instr.imm32);
|
||||
}
|
||||
emit(0xc88b480b75fffa83);
|
||||
emit(0x1274c9ff48c1d148);
|
||||
@ -661,7 +661,7 @@ namespace RandomX {
|
||||
if ((instr.locb & 7) <= 5) {
|
||||
emit(uint16_t(0x8141)); //cmp regb, imm32
|
||||
emitByte(0xf8 + (instr.regb % RegistersCount));
|
||||
emit(instr.imm1);
|
||||
emit(instr.imm32);
|
||||
if ((instr.locc & 7) <= 3) {
|
||||
emit(uint16_t(0x1676)); //jmp
|
||||
}
|
||||
@ -673,7 +673,7 @@ namespace RandomX {
|
||||
}
|
||||
emitByte(0x50); //push rax
|
||||
emitByte(0xe8); //call
|
||||
i = wrapInstr(i + (instr.imm0 & 127) + 2);
|
||||
i = wrapInstr(i + (instr.imm8 & 127) + 2);
|
||||
if (i < instructionOffsets.size()) {
|
||||
emit(instructionOffsets[i] - (codePos + 4));
|
||||
}
|
||||
@ -697,7 +697,7 @@ namespace RandomX {
|
||||
if ((instr.locb & 7) <= 5) {
|
||||
emit(uint16_t(0x8141)); //cmp regb, imm32
|
||||
emitByte(0xf8 + (instr.regb % RegistersCount));
|
||||
emit(instr.imm1);
|
||||
emit(instr.imm32);
|
||||
emitByte(0x77); //jmp
|
||||
emitByte(11 + crlen);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user