tevador
923420f0a3
Fixed mining and verification mode not giving the same results
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Trace support in Assembly generator
2019-02-16 23:18:45 +01:00
tevador
447e8a1d4f
Simplified division in interpreted mode
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Fixed incorrect condition code in JitCompilerX86
Refactoring
2019-02-15 10:41:02 +01:00
tevador
f76e8c2e20
Reworked "FNEG" instruction to make ASIC optimizations more difficult
2019-02-13 00:01:34 +01:00
tevador
b8ce504be6
Added comments to hashAes1Rx4 and fillAes1Rx4
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Fixed gcc compilation
Added performance numbers
2019-02-09 19:32:53 +01:00
tevador
2798d78717
Render imm32 as signed in RandomX code
2019-02-09 16:19:15 +01:00
tevador
32d827d0a6
Interpreter with bytecode
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Fixed some undefined behavior with signed types
Fixed different results on big endian systems
Removed unused code files
Restored FNEG_R instructions
Updated documentation
2019-02-09 15:45:26 +01:00
tevador
a586751f6b
Removed FPNEG instruction
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Optimized instruction frequencies
Increased the range for A registers from [1,65536) to [1, 4294967296)
2019-02-07 16:11:27 +01:00
tevador
ac4462ad42
Renamed floating point instructions
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Fixed negative source operand for FMUL_M and FDIV_M
2019-02-05 23:43:57 +01:00
tevador
b417fd08ea
16 -> 8 chained programs
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constant address loads are always from L3
2019-02-05 23:06:44 +01:00
tevador
1ee94bef2a
Added ISWAP instruction
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Scratchpad -> 2 MiB
New scratchpad initialization
New dataset initialization
2019-02-04 17:07:00 +01:00
tevador
8f2abd6c05
NOP instruction
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register load/store from L3
2019-01-27 18:19:49 +01:00
tevador
005c67f64c
Added explicit STORE instructions
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JIT compiler
2019-01-27 10:52:30 +01:00
tevador
d2cb086221
ASM code generator for "small" programs that fit into the uOP cache
2019-01-24 19:29:59 +01:00
tevador
16db607025
Scratchpad size increased to 1 MiB
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New AES-based scratchpad hashing function
2019-01-18 23:51:18 +01:00
tevador
8b1102ee05
Interpreter + async mode
2019-01-15 00:01:11 +01:00
tevador
a7ffe8c19a
Mix dataset cacheline with registers r0-r7
2019-01-13 21:14:59 +01:00
tevador
67e741ff22
Reduced x86 code size by 512 bytes (and ecx -> and eax)
2019-01-12 20:27:35 +01:00
tevador
1426fcbab5
Print average program code size
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Fixed assembly for MUL_64 and IMUL_32
Division weight 4 -> 8
2019-01-12 16:05:09 +01:00
tevador
2756bcdcfe
Added magic division to JIT compiler
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New B operand selection rules
2019-01-11 16:53:52 +01:00
tevador
451dfc5730
Optimized division by constants
2019-01-11 14:08:21 +01:00
tevador
c02ee4291d
FPROUND - variable flag offset
2019-01-11 10:52:12 +01:00
tevador
e487092f07
Simplified CALL and RET
2019-01-11 10:18:24 +01:00
tevador
557241cd95
JUMP instruction
2019-01-11 09:58:06 +01:00
tevador
d1a808643d
Random accesses - JIT compiler
2019-01-10 22:04:55 +01:00
tevador
b71e0eec65
Optimizations to reduce code size under 32K
2019-01-08 14:50:31 +01:00
tevador
b6d654291f
90 address transformations
2019-01-08 12:19:19 +01:00
tevador
2f6a599ff6
Inlined calls for memory read
2019-01-07 17:44:43 +01:00
tevador
619bee5418
Random dataset accesses - asm only
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Initial support for large pages
2019-01-04 19:44:15 +01:00
tevador
3caecc7646
Vector FPU instructions
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JitCompilerX86 - static code written in asm
Updated ALU/FPU tests
Updated instruction weights
2018-12-31 19:06:45 +01:00
tevador
a09bee8d60
js -> jz to enable macro-op fusion on Intel CPUs (~1% speed-up)
2018-12-28 14:18:41 +01:00
tevador
76b6b05cf2
Unconditional RET
2018-12-28 12:09:37 +01:00
tevador
740c40b218
8 branch conditions for CALL/RET
2018-12-21 22:41:35 +01:00
tevador
1db7dd6e8b
Renamed immediate constants
2018-12-20 18:36:09 +01:00
tevador
ed0bc906d6
JIT compiler for x86
2018-12-18 22:00:58 +01:00
tevador
4f276541d2
Modified x86 register allocation
2018-12-16 13:43:18 +01:00
tevador
6332831ec1
Implemented cache shift
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Fixed assembly code generator
Fixed an error in the interpreter
Updated specification: sign-extended immediates
2018-12-15 23:13:17 +01:00
tevador
cb0721056a
Assembly code generator for Windows 64-bit
2018-12-13 23:11:55 +01:00
