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c40ab9b5be
@ -24,7 +24,7 @@ enum V4_Settings
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enum V4_InstructionList
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{
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MUL, // a*b
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ADD, // a+b + C, -128 <= C <= 127
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ADD, // a+b + C, C is an unsigned 32-bit constant
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SUB, // a-b
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ROR, // rotate right "a" by "b & 31" bits
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ROL, // rotate left "a" by "b & 31" bits
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@ -215,7 +215,7 @@ static inline int v4_random_math_init(struct V4_Instruction* code, const uint64_
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//
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// Registers R4-R7 are constant and are treated as having the same value because when we do
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// the same operation twice with two constant source registers, it can be optimized into a single operation
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int inst_data[8] = { 0, 1, 2, 3, -1, -1, -1, -1 };
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uint32_t inst_data[8] = { 0, 1, 2, 3, 0xFFFFFF, 0xFFFFFF, 0xFFFFFF, 0xFFFFFF };
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bool alu_busy[TOTAL_LATENCY + 1][ALU_COUNT];
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bool is_rotation[V4_INSTRUCTION_COUNT];
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@ -233,10 +233,17 @@ static inline int v4_random_math_init(struct V4_Instruction* code, const uint64_
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int num_retries = 0;
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code_size = 0;
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int total_iterations = 0;
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// Generate random code to achieve minimal required latency for our abstract CPU
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// Try to get this latency for all 4 registers
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while (((latency[0] < TOTAL_LATENCY) || (latency[1] < TOTAL_LATENCY) || (latency[2] < TOTAL_LATENCY) || (latency[3] < TOTAL_LATENCY)) && (num_retries < 64))
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{
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// Fail-safe to guarantee loop termination
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++total_iterations;
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if (total_iterations > 256)
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break;
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check_data(&data_index, 1, data, sizeof(data));
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const uint8_t c = ((uint8_t*)data)[data_index++];
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