mirror of
https://git.wownero.com/wownero/RandomWOW.git
synced 2024-12-23 00:08:52 +00:00
736 lines
25 KiB
C++
736 lines
25 KiB
C++
/*
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Copyright (c) 2018 tevador
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This file is part of RandomX.
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RandomX is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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RandomX is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with RandomX. If not, see<http://www.gnu.org/licenses/>.
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*/
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//#define TRACE
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#include <climits>
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#include "assembly_generator_x86.hpp"
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#include "common.hpp"
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#include "reciprocal.h"
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#include "program.hpp"
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#include "superscalar.hpp"
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namespace randomx {
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static const char* regR[8] = { "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" };
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static const char* regR32[8] = { "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" };
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static const char* regFE[8] = { "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7" };
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static const char* regF[4] = { "xmm0", "xmm1", "xmm2", "xmm3" };
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static const char* regE[4] = { "xmm4", "xmm5", "xmm6", "xmm7" };
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static const char* regA[4] = { "xmm8", "xmm9", "xmm10", "xmm11" };
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static const char* regA4 = "xmm12";
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static const char* dblMin = "xmm13";
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static const char* absMask = "xmm14";
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static const char* signMask = "xmm15";
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static const char* regMx = "rbp";
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static const char* regIc = "rbx";
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static const char* regIc32 = "ebx";
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static const char* regIc8 = "bl";
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static const char* regDatasetAddr = "rdi";
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static const char* regScratchpadAddr = "rsi";
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void AssemblyGeneratorX86::generateProgram(Program& prog) {
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for (unsigned i = 0; i < 8; ++i) {
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registerUsage[i] = -1;
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}
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asmCode.str(std::string()); //clear
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for (unsigned i = 0; i < prog.getSize(); ++i) {
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asmCode << "randomx_isn_" << i << ":" << std::endl;
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Instruction& instr = prog(i);
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instr.src %= RegistersCount;
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instr.dst %= RegistersCount;
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generateCode(instr, i);
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}
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}
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void AssemblyGeneratorX86::generateAsm(SuperscalarProgram& prog) {
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asmCode.str(std::string()); //clear
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asmCode << "ALIGN 16" << std::endl;
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for (unsigned i = 0; i < prog.getSize(); ++i) {
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Instruction& instr = prog(i);
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switch (instr.opcode)
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{
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case SuperscalarInstructionType::ISUB_R:
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asmCode << "sub " << regR[instr.dst] << ", " << regR[instr.src] << std::endl;
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break;
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case SuperscalarInstructionType::IXOR_R:
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asmCode << "xor " << regR[instr.dst] << ", " << regR[instr.src] << std::endl;
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break;
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case SuperscalarInstructionType::IADD_RS:
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asmCode << "lea " << regR[instr.dst] << ", [" << regR[instr.dst] << "+" << regR[instr.src] << "*" << (1 << (instr.getModShift2())) << "]" << std::endl;
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break;
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case SuperscalarInstructionType::IMUL_R:
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asmCode << "imul " << regR[instr.dst] << ", " << regR[instr.src] << std::endl;
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break;
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case SuperscalarInstructionType::IROR_C:
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asmCode << "ror " << regR[instr.dst] << ", " << instr.getImm32() << std::endl;
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break;
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case SuperscalarInstructionType::IADD_C7:
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asmCode << "add " << regR[instr.dst] << ", " << (int32_t)instr.getImm32() << std::endl;
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break;
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case SuperscalarInstructionType::IXOR_C7:
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asmCode << "xor " << regR[instr.dst] << ", " << (int32_t)instr.getImm32() << std::endl;
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break;
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case SuperscalarInstructionType::IADD_C8:
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asmCode << "add " << regR[instr.dst] << ", " << (int32_t)instr.getImm32() << std::endl;
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asmCode << "nop" << std::endl;
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break;
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case SuperscalarInstructionType::IXOR_C8:
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asmCode << "xor " << regR[instr.dst] << ", " << (int32_t)instr.getImm32() << std::endl;
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asmCode << "nop" << std::endl;
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break;
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case SuperscalarInstructionType::IADD_C9:
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asmCode << "add " << regR[instr.dst] << ", " << (int32_t)instr.getImm32() << std::endl;
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asmCode << "xchg ax, ax ;nop" << std::endl;
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break;
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case SuperscalarInstructionType::IXOR_C9:
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asmCode << "xor " << regR[instr.dst] << ", " << (int32_t)instr.getImm32() << std::endl;
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asmCode << "xchg ax, ax ;nop" << std::endl;
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break;
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case SuperscalarInstructionType::IMULH_R:
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asmCode << "mov rax, " << regR[instr.dst] << std::endl;
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asmCode << "mul " << regR[instr.src] << std::endl;
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asmCode << "mov " << regR[instr.dst] << ", rdx" << std::endl;
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break;
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case SuperscalarInstructionType::ISMULH_R:
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asmCode << "mov rax, " << regR[instr.dst] << std::endl;
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asmCode << "imul " << regR[instr.src] << std::endl;
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asmCode << "mov " << regR[instr.dst] << ", rdx" << std::endl;
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break;
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case SuperscalarInstructionType::IMUL_RCP:
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asmCode << "mov rax, " << (int64_t)randomx_reciprocal(instr.getImm32()) << std::endl;
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asmCode << "imul " << regR[instr.dst] << ", rax" << std::endl;
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break;
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default:
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UNREACHABLE;
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}
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}
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}
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void AssemblyGeneratorX86::generateC(SuperscalarProgram& prog) {
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asmCode.str(std::string()); //clear
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asmCode << "#include <stdint.h>" << std::endl;
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asmCode << "#if defined(__SIZEOF_INT128__)" << std::endl;
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asmCode << " static inline uint64_t mulh(uint64_t a, uint64_t b) {" << std::endl;
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asmCode << " return ((unsigned __int128)a * b) >> 64;" << std::endl;
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asmCode << " }" << std::endl;
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asmCode << " static inline int64_t smulh(int64_t a, int64_t b) {" << std::endl;
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asmCode << " return ((__int128)a * b) >> 64;" << std::endl;
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asmCode << " }" << std::endl;
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asmCode << " #define HAVE_MULH" << std::endl;
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asmCode << " #define HAVE_SMULH" << std::endl;
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asmCode << "#endif" << std::endl;
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asmCode << "#if defined(_MSC_VER)" << std::endl;
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asmCode << " #define HAS_VALUE(X) X ## 0" << std::endl;
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asmCode << " #define EVAL_DEFINE(X) HAS_VALUE(X)" << std::endl;
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asmCode << " #include <intrin.h>" << std::endl;
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asmCode << " #include <stdlib.h>" << std::endl;
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asmCode << " static __inline uint64_t rotr(uint64_t x , int c) {" << std::endl;
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asmCode << " return _rotr64(x, c);" << std::endl;
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asmCode << " }" << std::endl;
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asmCode << " #define HAVE_ROTR" << std::endl;
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asmCode << " #if EVAL_DEFINE(__MACHINEARM64_X64(1))" << std::endl;
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asmCode << " static __inline uint64_t mulh(uint64_t a, uint64_t b) {" << std::endl;
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asmCode << " return __umulh(a, b);" << std::endl;
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asmCode << " }" << std::endl;
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asmCode << " #define HAVE_MULH" << std::endl;
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asmCode << " #endif" << std::endl;
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asmCode << " #if EVAL_DEFINE(__MACHINEX64(1))" << std::endl;
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asmCode << " static __inline int64_t smulh(int64_t a, int64_t b) {" << std::endl;
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asmCode << " int64_t hi;" << std::endl;
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asmCode << " _mul128(a, b, &hi);" << std::endl;
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asmCode << " return hi;" << std::endl;
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asmCode << " }" << std::endl;
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asmCode << " #define HAVE_SMULH" << std::endl;
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asmCode << " #endif" << std::endl;
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asmCode << "#endif" << std::endl;
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asmCode << "#ifndef HAVE_ROTR" << std::endl;
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asmCode << " static inline uint64_t rotr(uint64_t a, int b) {" << std::endl;
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asmCode << " return (a >> b) | (a << (64 - b));" << std::endl;
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asmCode << " }" << std::endl;
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asmCode << " #define HAVE_ROTR" << std::endl;
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asmCode << "#endif" << std::endl;
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asmCode << "#if !defined(HAVE_MULH) || !defined(HAVE_SMULH) || !defined(HAVE_ROTR)" << std::endl;
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asmCode << " #error \"Required functions are not defined\"" << std::endl;
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asmCode << "#endif" << std::endl;
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asmCode << "void superScalar(uint64_t r[8]) {" << std::endl;
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asmCode << "uint64_t r8 = r[0], r9 = r[1], r10 = r[2], r11 = r[3], r12 = r[4], r13 = r[5], r14 = r[6], r15 = r[7];" << std::endl;
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for (unsigned i = 0; i < prog.getSize(); ++i) {
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Instruction& instr = prog(i);
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switch (instr.opcode)
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{
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case SuperscalarInstructionType::ISUB_R:
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asmCode << regR[instr.dst] << " -= " << regR[instr.src] << ";" << std::endl;
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break;
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case SuperscalarInstructionType::IXOR_R:
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asmCode << regR[instr.dst] << " ^= " << regR[instr.src] << ";" << std::endl;
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break;
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case SuperscalarInstructionType::IADD_RS:
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asmCode << regR[instr.dst] << " += " << regR[instr.src] << "*" << (1 << (instr.getModShift2())) << ";" << std::endl;
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break;
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case SuperscalarInstructionType::IMUL_R:
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asmCode << regR[instr.dst] << " *= " << regR[instr.src] << ";" << std::endl;
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break;
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case SuperscalarInstructionType::IROR_C:
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asmCode << regR[instr.dst] << " = rotr(" << regR[instr.dst] << ", " << instr.getImm32() << ");" << std::endl;
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break;
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case SuperscalarInstructionType::IADD_C7:
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case SuperscalarInstructionType::IADD_C8:
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case SuperscalarInstructionType::IADD_C9:
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asmCode << regR[instr.dst] << " += " << (int32_t)instr.getImm32() << ";" << std::endl;
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break;
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case SuperscalarInstructionType::IXOR_C7:
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case SuperscalarInstructionType::IXOR_C8:
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case SuperscalarInstructionType::IXOR_C9:
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asmCode << regR[instr.dst] << " ^= " << (int32_t)instr.getImm32() << ";" << std::endl;
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break;
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case SuperscalarInstructionType::IMULH_R:
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asmCode << regR[instr.dst] << " = mulh(" << regR[instr.dst] << ", " << regR[instr.src] << ");" << std::endl;
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break;
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case SuperscalarInstructionType::ISMULH_R:
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asmCode << regR[instr.dst] << " = smulh(" << regR[instr.dst] << ", " << regR[instr.src] << ");" << std::endl;
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break;
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case SuperscalarInstructionType::IMUL_RCP:
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asmCode << regR[instr.dst] << " *= " << (int64_t)randomx_reciprocal(instr.getImm32()) << ";" << std::endl;
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break;
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default:
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UNREACHABLE;
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}
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}
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asmCode << "r[0] = r8; r[1] = r9; r[2] = r10; r[3] = r11; r[4] = r12; r[5] = r13; r[6] = r14; r[7] = r15;" << std::endl;
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asmCode << "}" << std::endl;
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}
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int AssemblyGeneratorX86::getConditionRegister() {
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int min = INT_MAX;
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int minIndex;
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for (unsigned i = 0; i < 8; ++i) {
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if (registerUsage[i] < min) {
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min = registerUsage[i];
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minIndex = i;
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}
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}
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return minIndex;
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}
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void AssemblyGeneratorX86::traceint(Instruction& instr) {
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if (trace) {
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asmCode << "\tpush " << regR[instr.dst] << std::endl;
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}
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}
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void AssemblyGeneratorX86::traceflt(Instruction& instr) {
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if (trace) {
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asmCode << "\tpush 0" << std::endl;
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}
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}
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void AssemblyGeneratorX86::tracenop(Instruction& instr) {
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if (trace) {
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asmCode << "\tpush 0" << std::endl;
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}
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}
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void AssemblyGeneratorX86::generateCode(Instruction& instr, int i) {
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asmCode << "\t; " << instr;
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auto generator = engine[instr.opcode];
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(this->*generator)(instr, i);
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}
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void AssemblyGeneratorX86::genAddressReg(Instruction& instr, const char* reg = "eax") {
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asmCode << "\tlea " << reg << ", [" << regR32[instr.src] << std::showpos << (int32_t)instr.getImm32() << std::noshowpos << "]" << std::endl;
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asmCode << "\tand " << reg << ", " << ((instr.getModMem()) ? ScratchpadL1Mask : ScratchpadL2Mask) << std::endl;
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}
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void AssemblyGeneratorX86::genAddressRegDst(Instruction& instr, int maskAlign = 8) {
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asmCode << "\tlea eax, [" << regR32[instr.dst] << std::showpos << (int32_t)instr.getImm32() << std::noshowpos << "]" << std::endl;
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int mask;
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if (instr.getModCond()) {
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mask = instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask;
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}
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else {
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mask = ScratchpadL3Mask;
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}
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asmCode << "\tand eax" << ", " << (mask & (-maskAlign)) << std::endl;
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}
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int32_t AssemblyGeneratorX86::genAddressImm(Instruction& instr) {
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return (int32_t)instr.getImm32() & ScratchpadL3Mask;
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}
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//1 uOP
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void AssemblyGeneratorX86::h_IADD_RS(Instruction& instr, int i) {
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registerUsage[instr.dst] = i;
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if(instr.dst == RegisterNeedsDisplacement)
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asmCode << "\tlea " << regR[instr.dst] << ", [" << regR[instr.dst] << "+" << regR[instr.src] << "*" << (1 << (instr.getModShift2())) << std::showpos << (int32_t)instr.getImm32() << std::noshowpos << "]" << std::endl;
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else
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asmCode << "\tlea " << regR[instr.dst] << ", [" << regR[instr.dst] << "+" << regR[instr.src] << "*" << (1 << (instr.getModShift2())) << "]" << std::endl;
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traceint(instr);
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}
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//2.75 uOP
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void AssemblyGeneratorX86::h_IADD_M(Instruction& instr, int i) {
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registerUsage[instr.dst] = i;
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if (instr.src != instr.dst) {
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genAddressReg(instr);
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asmCode << "\tadd " << regR[instr.dst] << ", qword ptr [rsi+rax]" << std::endl;
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}
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else {
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asmCode << "\tadd " << regR[instr.dst] << ", qword ptr [rsi+" << genAddressImm(instr) << "]" << std::endl;
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}
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traceint(instr);
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}
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//1 uOP
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void AssemblyGeneratorX86::h_IADD_RC(Instruction& instr, int i) {
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registerUsage[instr.dst] = i;
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asmCode << "\tlea " << regR[instr.dst] << ", [" << regR[instr.dst] << "+" << regR[instr.src] << std::showpos << (int32_t)instr.getImm32() << std::noshowpos << "]" << std::endl;
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traceint(instr);
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}
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//1 uOP
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void AssemblyGeneratorX86::h_ISUB_R(Instruction& instr, int i) {
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registerUsage[instr.dst] = i;
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if (instr.src != instr.dst) {
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asmCode << "\tsub " << regR[instr.dst] << ", " << regR[instr.src] << std::endl;
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}
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else {
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asmCode << "\tsub " << regR[instr.dst] << ", " << (int32_t)instr.getImm32() << std::endl;
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}
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traceint(instr);
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}
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//2.75 uOP
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void AssemblyGeneratorX86::h_ISUB_M(Instruction& instr, int i) {
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registerUsage[instr.dst] = i;
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if (instr.src != instr.dst) {
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genAddressReg(instr);
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asmCode << "\tsub " << regR[instr.dst] << ", qword ptr [rsi+rax]" << std::endl;
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}
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else {
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asmCode << "\tsub " << regR[instr.dst] << ", qword ptr [rsi+" << genAddressImm(instr) << "]" << std::endl;
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}
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traceint(instr);
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}
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//1 uOP
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void AssemblyGeneratorX86::h_IMUL_9C(Instruction& instr, int i) {
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registerUsage[instr.dst] = i;
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asmCode << "\tlea " << regR[instr.dst] << ", [" << regR[instr.dst] << "+" << regR[instr.dst] << "*8" << std::showpos << (int32_t)instr.getImm32() << std::noshowpos << "]" << std::endl;
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traceint(instr);
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}
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//1 uOP
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void AssemblyGeneratorX86::h_IMUL_R(Instruction& instr, int i) {
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registerUsage[instr.dst] = i;
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if (instr.src != instr.dst) {
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asmCode << "\timul " << regR[instr.dst] << ", " << regR[instr.src] << std::endl;
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}
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else {
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asmCode << "\timul " << regR[instr.dst] << ", " << (int32_t)instr.getImm32() << std::endl;
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}
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traceint(instr);
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}
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//2.75 uOP
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void AssemblyGeneratorX86::h_IMUL_M(Instruction& instr, int i) {
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registerUsage[instr.dst] = i;
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if (instr.src != instr.dst) {
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genAddressReg(instr);
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asmCode << "\timul " << regR[instr.dst] << ", qword ptr [rsi+rax]" << std::endl;
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}
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else {
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asmCode << "\timul " << regR[instr.dst] << ", qword ptr [rsi+" << genAddressImm(instr) << "]" << std::endl;
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}
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traceint(instr);
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}
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//4 uOPs
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void AssemblyGeneratorX86::h_IMULH_R(Instruction& instr, int i) {
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registerUsage[instr.dst] = i;
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asmCode << "\tmov rax, " << regR[instr.dst] << std::endl;
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asmCode << "\tmul " << regR[instr.src] << std::endl;
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asmCode << "\tmov " << regR[instr.dst] << ", rdx" << std::endl;
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traceint(instr);
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}
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//5.75 uOPs
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void AssemblyGeneratorX86::h_IMULH_M(Instruction& instr, int i) {
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registerUsage[instr.dst] = i;
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if (instr.src != instr.dst) {
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genAddressReg(instr, "ecx");
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asmCode << "\tmov rax, " << regR[instr.dst] << std::endl;
|
|
asmCode << "\tmul qword ptr [rsi+rcx]" << std::endl;
|
|
}
|
|
else {
|
|
asmCode << "\tmov rax, " << regR[instr.dst] << std::endl;
|
|
asmCode << "\tmul qword ptr [rsi+" << genAddressImm(instr) << "]" << std::endl;
|
|
}
|
|
asmCode << "\tmov " << regR[instr.dst] << ", rdx" << std::endl;
|
|
traceint(instr);
|
|
}
|
|
|
|
//4 uOPs
|
|
void AssemblyGeneratorX86::h_ISMULH_R(Instruction& instr, int i) {
|
|
registerUsage[instr.dst] = i;
|
|
asmCode << "\tmov rax, " << regR[instr.dst] << std::endl;
|
|
asmCode << "\timul " << regR[instr.src] << std::endl;
|
|
asmCode << "\tmov " << regR[instr.dst] << ", rdx" << std::endl;
|
|
traceint(instr);
|
|
}
|
|
|
|
//5.75 uOPs
|
|
void AssemblyGeneratorX86::h_ISMULH_M(Instruction& instr, int i) {
|
|
registerUsage[instr.dst] = i;
|
|
if (instr.src != instr.dst) {
|
|
genAddressReg(instr, "ecx");
|
|
asmCode << "\tmov rax, " << regR[instr.dst] << std::endl;
|
|
asmCode << "\timul qword ptr [rsi+rcx]" << std::endl;
|
|
}
|
|
else {
|
|
asmCode << "\tmov rax, " << regR[instr.dst] << std::endl;
|
|
asmCode << "\timul qword ptr [rsi+" << genAddressImm(instr) << "]" << std::endl;
|
|
}
|
|
asmCode << "\tmov " << regR[instr.dst] << ", rdx" << std::endl;
|
|
traceint(instr);
|
|
}
|
|
|
|
//1 uOP
|
|
void AssemblyGeneratorX86::h_INEG_R(Instruction& instr, int i) {
|
|
registerUsage[instr.dst] = i;
|
|
asmCode << "\tneg " << regR[instr.dst] << std::endl;
|
|
traceint(instr);
|
|
}
|
|
|
|
//1 uOP
|
|
void AssemblyGeneratorX86::h_IXOR_R(Instruction& instr, int i) {
|
|
registerUsage[instr.dst] = i;
|
|
if (instr.src != instr.dst) {
|
|
asmCode << "\txor " << regR[instr.dst] << ", " << regR[instr.src] << std::endl;
|
|
}
|
|
else {
|
|
asmCode << "\txor " << regR[instr.dst] << ", " << (int32_t)instr.getImm32() << std::endl;
|
|
}
|
|
traceint(instr);
|
|
}
|
|
|
|
//2.75 uOP
|
|
void AssemblyGeneratorX86::h_IXOR_M(Instruction& instr, int i) {
|
|
registerUsage[instr.dst] = i;
|
|
if (instr.src != instr.dst) {
|
|
genAddressReg(instr);
|
|
asmCode << "\txor " << regR[instr.dst] << ", qword ptr [rsi+rax]" << std::endl;
|
|
}
|
|
else {
|
|
asmCode << "\txor " << regR[instr.dst] << ", qword ptr [rsi+" << genAddressImm(instr) << "]" << std::endl;
|
|
}
|
|
traceint(instr);
|
|
}
|
|
|
|
//1.75 uOPs
|
|
void AssemblyGeneratorX86::h_IROR_R(Instruction& instr, int i) {
|
|
registerUsage[instr.dst] = i;
|
|
if (instr.src != instr.dst) {
|
|
asmCode << "\tmov ecx, " << regR32[instr.src] << std::endl;
|
|
asmCode << "\tror " << regR[instr.dst] << ", cl" << std::endl;
|
|
}
|
|
else {
|
|
asmCode << "\tror " << regR[instr.dst] << ", " << (instr.getImm32() & 63) << std::endl;
|
|
}
|
|
traceint(instr);
|
|
}
|
|
|
|
//1.75 uOPs
|
|
void AssemblyGeneratorX86::h_IROL_R(Instruction& instr, int i) {
|
|
registerUsage[instr.dst] = i;
|
|
if (instr.src != instr.dst) {
|
|
asmCode << "\tmov ecx, " << regR32[instr.src] << std::endl;
|
|
asmCode << "\trol " << regR[instr.dst] << ", cl" << std::endl;
|
|
}
|
|
else {
|
|
asmCode << "\trol " << regR[instr.dst] << ", " << (instr.getImm32() & 63) << std::endl;
|
|
}
|
|
traceint(instr);
|
|
}
|
|
|
|
//2 uOPs
|
|
void AssemblyGeneratorX86::h_IMUL_RCP(Instruction& instr, int i) {
|
|
if (instr.getImm32() != 0) {
|
|
registerUsage[instr.dst] = i;
|
|
uint32_t divisor = instr.getImm32();
|
|
asmCode << "\tmov rax, " << randomx_reciprocal(instr.getImm32()) << std::endl;
|
|
asmCode << "\timul " << regR[instr.dst] << ", rax" << std::endl;
|
|
traceint(instr);
|
|
}
|
|
else {
|
|
tracenop(instr);
|
|
}
|
|
}
|
|
|
|
//~8.5 uOPs
|
|
void AssemblyGeneratorX86::h_ISDIV_C(Instruction& instr, int i) {
|
|
tracenop(instr);
|
|
}
|
|
|
|
//2 uOPs
|
|
void AssemblyGeneratorX86::h_ISWAP_R(Instruction& instr, int i) {
|
|
if (instr.src != instr.dst) {
|
|
registerUsage[instr.dst] = i;
|
|
registerUsage[instr.src] = i;
|
|
asmCode << "\txchg " << regR[instr.dst] << ", " << regR[instr.src] << std::endl;
|
|
traceint(instr);
|
|
}
|
|
else {
|
|
tracenop(instr);
|
|
}
|
|
}
|
|
|
|
//1 uOPs
|
|
void AssemblyGeneratorX86::h_FSWAP_R(Instruction& instr, int i) {
|
|
asmCode << "\tshufpd " << regFE[instr.dst] << ", " << regFE[instr.dst] << ", 1" << std::endl;
|
|
traceflt(instr);
|
|
}
|
|
|
|
//1 uOP
|
|
void AssemblyGeneratorX86::h_FADD_R(Instruction& instr, int i) {
|
|
instr.dst %= 4;
|
|
instr.src %= 4;
|
|
asmCode << "\taddpd " << regF[instr.dst] << ", " << regA[instr.src] << std::endl;
|
|
traceflt(instr);
|
|
}
|
|
|
|
//5 uOPs
|
|
void AssemblyGeneratorX86::h_FADD_M(Instruction& instr, int i) {
|
|
instr.dst %= 4;
|
|
genAddressReg(instr);
|
|
asmCode << "\tcvtdq2pd xmm12, qword ptr [rsi+rax]" << std::endl;
|
|
asmCode << "\taddpd " << regF[instr.dst] << ", xmm12" << std::endl;
|
|
traceflt(instr);
|
|
}
|
|
|
|
//1 uOP
|
|
void AssemblyGeneratorX86::h_FSUB_R(Instruction& instr, int i) {
|
|
instr.dst %= 4;
|
|
instr.src %= 4;
|
|
asmCode << "\tsubpd " << regF[instr.dst] << ", " << regA[instr.src] << std::endl;
|
|
traceflt(instr);
|
|
}
|
|
|
|
//5 uOPs
|
|
void AssemblyGeneratorX86::h_FSUB_M(Instruction& instr, int i) {
|
|
instr.dst %= 4;
|
|
genAddressReg(instr);
|
|
asmCode << "\tcvtdq2pd xmm12, qword ptr [rsi+rax]" << std::endl;
|
|
asmCode << "\tsubpd " << regF[instr.dst] << ", xmm12" << std::endl;
|
|
traceflt(instr);
|
|
}
|
|
|
|
//1 uOP
|
|
void AssemblyGeneratorX86::h_FSCAL_R(Instruction& instr, int i) {
|
|
instr.dst %= 4;
|
|
asmCode << "\txorps " << regF[instr.dst] << ", " << signMask << std::endl;
|
|
traceflt(instr);
|
|
}
|
|
|
|
//1 uOPs
|
|
void AssemblyGeneratorX86::h_FMUL_R(Instruction& instr, int i) {
|
|
instr.dst %= 4;
|
|
instr.src %= 4;
|
|
asmCode << "\tmulpd " << regE[instr.dst] << ", " << regA[instr.src] << std::endl;
|
|
traceflt(instr);
|
|
}
|
|
|
|
//7 uOPs
|
|
void AssemblyGeneratorX86::h_FMUL_M(Instruction& instr, int i) {
|
|
instr.dst %= 4;
|
|
genAddressReg(instr);
|
|
asmCode << "\tcvtdq2pd xmm12, qword ptr [rsi+rax]" << std::endl;
|
|
asmCode << "\tandps xmm12, xmm14" << std::endl;
|
|
asmCode << "\tmulpd " << regE[instr.dst] << ", xmm12" << std::endl;
|
|
asmCode << "\tmaxpd " << regE[instr.dst] << ", " << dblMin << std::endl;
|
|
traceflt(instr);
|
|
}
|
|
|
|
//2 uOPs
|
|
void AssemblyGeneratorX86::h_FDIV_R(Instruction& instr, int i) {
|
|
instr.dst %= 4;
|
|
instr.src %= 4;
|
|
asmCode << "\tdivpd " << regE[instr.dst] << ", " << regA[instr.src] << std::endl;
|
|
asmCode << "\tmaxpd " << regE[instr.dst] << ", " << dblMin << std::endl;
|
|
traceflt(instr);
|
|
}
|
|
|
|
//7 uOPs
|
|
void AssemblyGeneratorX86::h_FDIV_M(Instruction& instr, int i) {
|
|
instr.dst %= 4;
|
|
genAddressReg(instr);
|
|
asmCode << "\tcvtdq2pd xmm12, qword ptr [rsi+rax]" << std::endl;
|
|
asmCode << "\tandps xmm12, xmm13" << std::endl;
|
|
asmCode << "\torps xmm12, xmm14" << std::endl;
|
|
asmCode << "\tdivpd " << regE[instr.dst] << ", xmm12" << std::endl;
|
|
traceflt(instr);
|
|
}
|
|
|
|
//1 uOP
|
|
void AssemblyGeneratorX86::h_FSQRT_R(Instruction& instr, int i) {
|
|
instr.dst %= 4;
|
|
asmCode << "\tsqrtpd " << regE[instr.dst] << ", " << regE[instr.dst] << std::endl;
|
|
traceflt(instr);
|
|
}
|
|
|
|
//6 uOPs
|
|
void AssemblyGeneratorX86::h_CFROUND(Instruction& instr, int i) {
|
|
asmCode << "\tmov rax, " << regR[instr.src] << std::endl;
|
|
int rotate = (13 - (instr.getImm32() & 63)) & 63;
|
|
if (rotate != 0)
|
|
asmCode << "\trol rax, " << rotate << std::endl;
|
|
asmCode << "\tand eax, 24576" << std::endl;
|
|
asmCode << "\tor eax, 40896" << std::endl;
|
|
asmCode << "\tmov dword ptr [rsp-8], eax" << std::endl;
|
|
asmCode << "\tldmxcsr dword ptr [rsp-8]" << std::endl;
|
|
tracenop(instr);
|
|
}
|
|
|
|
static inline const char* condition(Instruction& instr) {
|
|
switch (instr.getModCond())
|
|
{
|
|
case 0:
|
|
return "be";
|
|
case 1:
|
|
return "a";
|
|
case 2:
|
|
return "s";
|
|
case 3:
|
|
return "ns";
|
|
case 4:
|
|
return "o";
|
|
case 5:
|
|
return "no";
|
|
case 6:
|
|
return "l";
|
|
case 7:
|
|
return "ge";
|
|
default:
|
|
UNREACHABLE;
|
|
}
|
|
}
|
|
|
|
void AssemblyGeneratorX86::handleCondition(Instruction& instr, int i) {
|
|
const int shift = instr.getModShift3();
|
|
const int conditionMask = ((1 << RANDOMX_CONDITION_BITS) - 1) << shift;
|
|
int reg = getConditionRegister();
|
|
int target = registerUsage[reg] + 1;
|
|
registerUsage[reg] = i;
|
|
asmCode << "\tadd " << regR[reg] << ", " << (1 << shift) << std::endl;
|
|
asmCode << "\ttest " << regR[reg] << ", " << conditionMask << std::endl;
|
|
asmCode << "\tjz randomx_isn_" << target << std::endl;
|
|
for (unsigned j = 0; j < 8; ++j) { //mark all registers as used
|
|
registerUsage[j] = i;
|
|
}
|
|
}
|
|
|
|
//4 uOPs
|
|
void AssemblyGeneratorX86::h_COND_R(Instruction& instr, int i) {
|
|
handleCondition(instr, i);
|
|
asmCode << "\txor ecx, ecx" << std::endl;
|
|
asmCode << "\tcmp " << regR32[instr.src] << ", " << (int32_t)instr.getImm32() << std::endl;
|
|
asmCode << "\tset" << condition(instr) << " cl" << std::endl;
|
|
asmCode << "\tadd " << regR[instr.dst] << ", rcx" << std::endl;
|
|
traceint(instr);
|
|
}
|
|
|
|
//6 uOPs
|
|
void AssemblyGeneratorX86::h_COND_M(Instruction& instr, int i) {
|
|
handleCondition(instr, i);
|
|
asmCode << "\txor ecx, ecx" << std::endl;
|
|
genAddressReg(instr);
|
|
asmCode << "\tcmp dword ptr [rsi+rax], " << (int32_t)instr.getImm32() << std::endl;
|
|
asmCode << "\tset" << condition(instr) << " cl" << std::endl;
|
|
asmCode << "\tadd " << regR[instr.dst] << ", rcx" << std::endl;
|
|
traceint(instr);
|
|
}
|
|
|
|
//3 uOPs
|
|
void AssemblyGeneratorX86::h_ISTORE(Instruction& instr, int i) {
|
|
genAddressRegDst(instr);
|
|
asmCode << "\tmov qword ptr [rsi+rax], " << regR[instr.src] << std::endl;
|
|
tracenop(instr);
|
|
}
|
|
|
|
//3 uOPs
|
|
void AssemblyGeneratorX86::h_FSTORE(Instruction& instr, int i) {
|
|
genAddressRegDst(instr, 16);
|
|
asmCode << "\tmovapd xmmword ptr [rsi+rax], " << regFE[instr.src] << std::endl;
|
|
tracenop(instr);
|
|
}
|
|
|
|
void AssemblyGeneratorX86::h_NOP(Instruction& instr, int i) {
|
|
asmCode << "\tnop" << std::endl;
|
|
tracenop(instr);
|
|
}
|
|
|
|
#include "instruction_weights.hpp"
|
|
#define INST_HANDLE(x) REPN(&AssemblyGeneratorX86::h_##x, WT(x))
|
|
|
|
InstructionGenerator AssemblyGeneratorX86::engine[256] = {
|
|
//Integer
|
|
INST_HANDLE(IADD_RS)
|
|
INST_HANDLE(IADD_M)
|
|
INST_HANDLE(IADD_RC)
|
|
INST_HANDLE(ISUB_R)
|
|
INST_HANDLE(ISUB_M)
|
|
INST_HANDLE(IMUL_9C)
|
|
INST_HANDLE(IMUL_R)
|
|
INST_HANDLE(IMUL_M)
|
|
INST_HANDLE(IMULH_R)
|
|
INST_HANDLE(IMULH_M)
|
|
INST_HANDLE(ISMULH_R)
|
|
INST_HANDLE(ISMULH_M)
|
|
INST_HANDLE(IMUL_RCP)
|
|
INST_HANDLE(INEG_R)
|
|
INST_HANDLE(IXOR_R)
|
|
INST_HANDLE(IXOR_M)
|
|
INST_HANDLE(IROR_R)
|
|
INST_HANDLE(IROL_R)
|
|
INST_HANDLE(ISWAP_R)
|
|
|
|
//Common floating point
|
|
INST_HANDLE(FSWAP_R)
|
|
|
|
//Floating point group F
|
|
INST_HANDLE(FADD_R)
|
|
INST_HANDLE(FADD_M)
|
|
INST_HANDLE(FSUB_R)
|
|
INST_HANDLE(FSUB_M)
|
|
INST_HANDLE(FSCAL_R)
|
|
|
|
//Floating point group E
|
|
INST_HANDLE(FMUL_R)
|
|
INST_HANDLE(FDIV_M)
|
|
INST_HANDLE(FSQRT_R)
|
|
|
|
//Control
|
|
INST_HANDLE(COND_R)
|
|
INST_HANDLE(COND_M)
|
|
INST_HANDLE(CFROUND)
|
|
INST_HANDLE(ISTORE)
|
|
|
|
INST_HANDLE(NOP)
|
|
};
|
|
} |