7 Commits

Author	SHA1	Message	Date
tevador	d9bc6cfeda	Updated JIT compiler and assembly generator for new int -> float conversion	2019-02-24 17:24:06 +01:00
tevador	f3b114af88	Replaced division instructions with IMUL_RCP	2019-02-22 17:48:26 +01:00
tevador	f76e8c2e20	Reworked "FNEG" instruction to make ASIC optimizations more difficult	2019-02-13 00:01:34 +01:00
tevador	9af0cbf108	Documentation formatting	2019-02-09 16:09:55 +01:00
tevador	32d827d0a6	Interpreter with bytecode ... Fixed some undefined behavior with signed types Fixed different results on big endian systems Removed unused code files Restored FNEG_R instructions Updated documentation	2019-02-09 15:45:26 +01:00
tevador	c02ee4291d	FPROUND - variable flag offset	2019-01-11 10:52:12 +01:00
tevador	6941b2cb69	Reworked instruction set documentation	2019-01-10 23:36:53 +01:00