90 address transformations

src/AssemblyGeneratorX86.cpp

@@ -28,7 +28,7 @@ namespace RandomX {
 	static const char* regR32[8] = { "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" };
 	static const char* regF[8] = { "xmm8", "xmm9", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7" };
 
-	static const char* regMx = "edi";
+	static const char* regMx = "rdi";
 	static const char* regIc = "ebp";
 	static const char* regStackBeginAddr = "rbx";
 	static const char* regScratchpadAddr = "rsi";
@@ -62,7 +62,7 @@ namespace RandomX {
 	void AssemblyGeneratorX86::genar(Instruction& instr, int i) {
 		asmCode << "\txor " << regR[instr.rega % RegistersCount] << ", 0" << std::hex << instr.addra << "h" << std::dec << std::endl;
 		asmCode << "\tmov ecx, " << regR32[instr.rega % RegistersCount] << std::endl;
-		asmCode << "\ttest ebp, 63" << std::endl;
+		asmCode << "\ttest " << regIc << ", 63" << std::endl;
 		asmCode << "\tjnz short rx_body_" << i << std::endl;
 		switch (instr.loca & 3)
 		{
@@ -71,24 +71,24 @@ namespace RandomX {
 			case 2:
 				asmCode << "\tcall rx_read_l1" << std::endl;
 				asmCode << "rx_body_" << i << ":" << std::endl;
-				asmCode << "\txor rdi, rcx" << std::endl;
+				asmCode << "\txor " << regMx << ", rcx" << std::endl;
 				asmCode << "\tand ecx, " << (ScratchpadL1 - 1) << std::endl;
 				break;
 			default: //3
 				asmCode << "\tcall rx_read_l2" << std::endl;
 				asmCode << "rx_body_" << i << ":" << std::endl;
-				asmCode << "\txor rdi, rcx" << std::endl;
+				asmCode << "\txor " << regMx << ", rcx" << std::endl;
 				asmCode << "\tand ecx, " << (ScratchpadL2 - 1) << std::endl;
 				break;
 		}
-		asmCode << "\tmov rax, qword ptr [rsi+rcx*8]" << std::endl;
+		asmCode << "\tmov rax, qword ptr [" << regScratchpadAddr << "+rcx*8]" << std::endl;
 	}
 
 
 	void AssemblyGeneratorX86::genaf(Instruction& instr, int i) {
 		asmCode << "\txor " << regR[instr.rega % RegistersCount] << ", 0" << std::hex << instr.addra << "h" << std::dec << std::endl;
 		asmCode << "\tmov ecx, " << regR32[instr.rega % RegistersCount] << std::endl;
-		asmCode << "\ttest ebp, 63" << std::endl;
+		asmCode << "\ttest " << regIc << ", 63" << std::endl;
 		asmCode << "\tjnz short rx_body_" << i << std::endl;
 		switch (instr.loca & 3)
 		{
@@ -97,17 +97,17 @@ namespace RandomX {
 			case 2:
 				asmCode << "\tcall rx_read_l1" << std::endl;
 				asmCode << "rx_body_" << i << ":" << std::endl;
-				asmCode << "\txor rdi, rcx" << std::endl;
+				asmCode << "\txor " << regMx << ", rcx" << std::endl;
 				asmCode << "\tand ecx, " << (ScratchpadL1 - 1) << std::endl;
 				break;
 			default: //3
 				asmCode << "\tcall rx_read_l2" << std::endl;
 				asmCode << "rx_body_" << i << ":" << std::endl;
-				asmCode << "\txor rdi, rcx" << std::endl;
+				asmCode << "\txor " << regMx << ", rcx" << std::endl;
 				asmCode << "\tand ecx, " << (ScratchpadL2 - 1) << std::endl;
 				break;
 		}
-		asmCode << "\tcvtdq2pd xmm0, qword ptr [rsi+rcx*8]" << std::endl;
+		asmCode << "\tcvtdq2pd xmm0, qword ptr [" << regScratchpadAddr << "+rcx*8]" << std::endl;
 	}
 
 	void AssemblyGeneratorX86::genbr0(Instruction& instr, const char* instrx86) {
@@ -174,7 +174,7 @@ namespace RandomX {
 			asmCode << "\tand eax, " << (ScratchpadL2 - 1) << std::endl;
 			asmCode << "\tmov qword ptr [" << regScratchpadAddr << " + rax * 8], rcx" << std::endl;
 			if (trace) {
-				asmCode << "\tmov qword ptr [" << regScratchpadAddr << " + rdi * 8 + 262136], rcx" << std::endl;
+				asmCode << "\tmov qword ptr [" << regScratchpadAddr << " + " << regIc << " * 8 + 262136], rcx" << std::endl;
 			}
 			return;
 
@@ -187,14 +187,14 @@ namespace RandomX {
 			asmCode << "\tand eax, " << (ScratchpadL1 - 1) << std::endl;
 			asmCode << "\tmov qword ptr [" << regScratchpadAddr << " + rax * 8], rcx" << std::endl;
 			if (trace) {
-				asmCode << "\tmov qword ptr [" << regScratchpadAddr << " + rdi * 8 + 262136], rcx" << std::endl;
+				asmCode << "\tmov qword ptr [" << regScratchpadAddr << " + " << regIc << " * 8 + 262136], rcx" << std::endl;
 			}
 			return;
 
 		default:
 			asmCode << "\tmov " << regR[instr.regc % RegistersCount] << ", rax" << std::endl;
 			if (trace) {
-				asmCode << "\tmov qword ptr [" << regScratchpadAddr << " + rdi * 8 + 262136], rax" << std::endl;
+				asmCode << "\tmov qword ptr [" << regScratchpadAddr << " + " << regIc << " * 8 + 262136], rax" << std::endl;
 			}
 			return;
 		}
@@ -222,7 +222,7 @@ namespace RandomX {
 				break;
 		}
 		if (trace) {
-			asmCode << "\t" << store << " qword ptr [" << regScratchpadAddr << " + rdi * 8 + 262136], " << regF[instr.regc % RegistersCount] << std::endl;
+			asmCode << "\t" << store << " qword ptr [" << regScratchpadAddr << " + " << regIc << " * 8 + 262136], " << regF[instr.regc % RegistersCount] << std::endl;
 		}
 	}
 
@@ -498,7 +498,7 @@ namespace RandomX {
 		asmCode << "\tjmp rx_i_" << wrapInstr(i + 1) << std::endl;
 		asmCode << "taken_call_" << i << ":" << std::endl;
 		if (trace) {
-			asmCode << "\tmov qword ptr [" << regScratchpadAddr << " + rdi * 8 + 262136], rax" << std::endl;
+			asmCode << "\tmov qword ptr [" << regScratchpadAddr << " + " << regIc << " * 8 + 262136], rax" << std::endl;
 		}
 		asmCode << "\tpush rax" << std::endl;
 		asmCode << "\tcall rx_i_" << wrapInstr(i + (instr.imm8 & 127) + 2) << std::endl;

src/asm/program_transform_address.inc

@@ -0,0 +1,154 @@
+	;# 90 address transformations
+	;# forced REX prefix is used to make all transformations 4 bytes long
+	lea ecx, [rcx+rcx*8+109]
+	db 64
+	xor ecx, 96
+	lea ecx, [rcx+rcx*8-19]
+	db 64
+	add ecx, -98
+	db 64
+	add ecx, -21
+	db 64
+	xor ecx, -80
+	lea ecx, [rcx+rcx*8-92]
+	db 64
+	add ecx, 113
+	lea ecx, [rcx+rcx*8+100]
+	db 64
+	add ecx, -39
+	db 64
+	xor ecx, 120
+	lea ecx, [rcx+rcx*8-119]
+	db 64
+	add ecx, -113
+	db 64
+	add ecx, 111
+	db 64
+	xor ecx, 104
+	lea ecx, [rcx+rcx*8-83]
+	lea ecx, [rcx+rcx*8+127]
+	db 64
+	xor ecx, -112
+	db 64
+	add ecx, 89
+	db 64
+	add ecx, -32
+	db 64
+	add ecx, 104
+	db 64
+	xor ecx, -120
+	db 64
+	xor ecx, 24
+	lea ecx, [rcx+rcx*8+9]
+	db 64
+	add ecx, -31
+	db 64
+	xor ecx, -16
+	db 64
+	add ecx, 68
+	lea ecx, [rcx+rcx*8-110]
+	db 64
+	xor ecx, 64
+	db 64
+	xor ecx, -40
+	db 64
+	xor ecx, -8
+	db 64
+	add ecx, -10
+	db 64
+	xor ecx, -32
+	db 64
+	add ecx, 14
+	lea ecx, [rcx+rcx*8-46]
+	db 64
+	xor ecx, -104
+	lea ecx, [rcx+rcx*8+36]
+	db 64
+	add ecx, 100
+	lea ecx, [rcx+rcx*8-65]
+	lea ecx, [rcx+rcx*8+27]
+	lea ecx, [rcx+rcx*8+91]
+	db 64
+	add ecx, -101
+	db 64
+	add ecx, -94
+	lea ecx, [rcx+rcx*8-10]
+	db 64
+	xor ecx, 80
+	db 64
+	add ecx, -108
+	db 64
+	add ecx, -58
+	db 64
+	xor ecx, 48
+	lea ecx, [rcx+rcx*8+73]
+	db 64
+	xor ecx, -48
+	db 64
+	xor ecx, 32
+	db 64
+	xor ecx, -96
+	db 64
+	add ecx, 118
+	db 64
+	add ecx, 91
+	lea ecx, [rcx+rcx*8+18]
+	db 64
+	add ecx, -11
+	lea ecx, [rcx+rcx*8+63]
+	db 64
+	add ecx, 114
+	lea ecx, [rcx+rcx*8+45]
+	db 64
+	add ecx, -67
+	db 64
+	add ecx, 53
+	lea ecx, [rcx+rcx*8-101]
+	lea ecx, [rcx+rcx*8-1]
+	db 64
+	xor ecx, 16
+	lea ecx, [rcx+rcx*8-37]
+	lea ecx, [rcx+rcx*8-28]
+	lea ecx, [rcx+rcx*8-55]
+	db 64
+	xor ecx, -88
+	db 64
+	xor ecx, -72
+	db 64
+	add ecx, 36
+	db 64
+	xor ecx, -56
+	db 64
+	add ecx, 116
+	db 64
+	xor ecx, 88
+	db 64
+	xor ecx, -128
+	db 64
+	add ecx, 50
+	db 64
+	add ecx, 105
+	db 64
+	add ecx, -37
+	db 64
+	xor ecx, 112
+	db 64
+	xor ecx, 8
+	db 64
+	xor ecx, -24
+	lea ecx, [rcx+rcx*8+118]
+	db 64
+	xor ecx, 72
+	db 64
+	xor ecx, -64
+	db 64
+	add ecx, 40
+	lea ecx, [rcx+rcx*8-74]
+	lea ecx, [rcx+rcx*8+82]
+	lea ecx, [rcx+rcx*8+54]
+	db 64
+	xor ecx, 56
+	db 64
+	xor ecx, 40
+	db 64
+	add ecx, 87