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js -> jz to enable macro-op fusion on Intel CPUs (~1% speed-up)
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@ -49,7 +49,7 @@ namespace RandomX {
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void AssemblyGeneratorX86::generateCode(Instruction& instr, int i) {
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void AssemblyGeneratorX86::generateCode(Instruction& instr, int i) {
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asmCode << "rx_i_" << i << ": ;" << instr.getName() << std::endl;
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asmCode << "rx_i_" << i << ": ;" << instr.getName() << std::endl;
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asmCode << "\tdec edi" << std::endl;
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asmCode << "\tdec edi" << std::endl;
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asmCode << "\tjs rx_finish" << std::endl;
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asmCode << "\tjz rx_finish" << std::endl;
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auto generator = engine[instr.opcode];
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auto generator = engine[instr.opcode];
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(this->*generator)(instr, i);
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(this->*generator)(instr, i);
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}
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}
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@ -81,10 +81,10 @@ namespace RandomX {
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*/
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*/
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constexpr uint8_t ic3 = (InstructionCount >> 24);
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constexpr uint8_t ic3 = ((InstructionCount + 1) >> 24);
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constexpr uint8_t ic2 = (InstructionCount >> 16);
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constexpr uint8_t ic2 = ((InstructionCount + 1) >> 16);
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constexpr uint8_t ic1 = (InstructionCount >> 8);
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constexpr uint8_t ic1 = ((InstructionCount + 1) >> 8);
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constexpr uint8_t ic0 = (InstructionCount >> 0);
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constexpr uint8_t ic0 = ((InstructionCount + 1) >> 0);
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const uint8_t prologue[] = {
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const uint8_t prologue[] = {
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0x53, //push rbx
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0x53, //push rbx
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@ -245,7 +245,7 @@ namespace RandomX {
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void JitCompilerX86::generateCode(Instruction& instr, int i) {
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void JitCompilerX86::generateCode(Instruction& instr, int i) {
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instructionOffsets.push_back(codePos);
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instructionOffsets.push_back(codePos);
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emit(0x880fcfff); //dec edx; js <epilogue>
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emit(0x840fcfff); //dec edx; jz <epilogue>
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emit(epilogueOffset - (codePos + 4)); //jump offset (RIP-relative)
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emit(epilogueOffset - (codePos + 4)); //jump offset (RIP-relative)
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gena(instr);
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gena(instr);
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auto generator = engine[instr.opcode];
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auto generator = engine[instr.opcode];
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@ -84,7 +84,7 @@ executeProgram PROC
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push r9
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push r9
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mov rbp, rsp ; beginning of VM stack
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mov rbp, rsp ; beginning of VM stack
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mov rdi, 1048576 ; number of VM instructions to execute
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mov rdi, 1048577 ; number of VM instructions to execute + 1
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; load VM register values
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; load VM register values
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mov r8, qword ptr [rcx+0]
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mov r8, qword ptr [rcx+0]
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