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https://git.wownero.com/wownero/RandomWOW.git
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JUMP instruction
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parent
6941b2cb69
commit
557241cd95
@ -496,6 +496,14 @@ namespace RandomX {
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}
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}
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}
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}
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void AssemblyGeneratorX86::h_JUMP(Instruction& instr, int i) {
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genar(instr, i);
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gencr(instr);
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asmCode << "\tcmp " << regR32[instr.regb % RegistersCount] << ", " << instr.imm32 << std::endl;
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asmCode << "\t" << jumpCondition(instr);
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asmCode << " rx_i_" << wrapInstr(i + (instr.imm8 & 127) + 2) << std::endl;
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}
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void AssemblyGeneratorX86::h_CALL(Instruction& instr, int i) {
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void AssemblyGeneratorX86::h_CALL(Instruction& instr, int i) {
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genar(instr, i);
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genar(instr, i);
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asmCode << "\tcmp " << regR32[instr.regb % RegistersCount] << ", " << instr.imm32 << std::endl;
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asmCode << "\tcmp " << regR32[instr.regb % RegistersCount] << ", " << instr.imm32 << std::endl;
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@ -554,6 +562,7 @@ namespace RandomX {
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INST_HANDLE(FPDIV)
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INST_HANDLE(FPDIV)
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INST_HANDLE(FPSQRT)
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INST_HANDLE(FPSQRT)
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INST_HANDLE(FPROUND)
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INST_HANDLE(FPROUND)
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INST_HANDLE(JUMP)
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INST_HANDLE(CALL)
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INST_HANDLE(CALL)
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INST_HANDLE(RET)
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INST_HANDLE(RET)
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};
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};
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@ -77,6 +77,7 @@ namespace RandomX {
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void h_FPDIV(Instruction&, int);
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void h_FPDIV(Instruction&, int);
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void h_FPSQRT(Instruction&, int);
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void h_FPSQRT(Instruction&, int);
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void h_FPROUND(Instruction&, int);
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void h_FPROUND(Instruction&, int);
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void h_JUMP(Instruction&, int);
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void h_CALL(Instruction&, int);
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void h_CALL(Instruction&, int);
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void h_RET(Instruction&, int);
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void h_RET(Instruction&, int);
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};
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};
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@ -63,6 +63,7 @@ namespace RandomX {
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INST_NAME(FPDIV)
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INST_NAME(FPDIV)
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INST_NAME(FPSQRT)
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INST_NAME(FPSQRT)
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INST_NAME(FPROUND)
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INST_NAME(FPROUND)
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INST_NAME(JUMP)
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INST_NAME(CALL)
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INST_NAME(CALL)
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INST_NAME(RET)
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INST_NAME(RET)
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};
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};
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@ -603,6 +603,24 @@ namespace RandomX {
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}
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}
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}
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}
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void JitCompilerX86::h_JUMP(Instruction& instr, int i) {
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genar(instr);
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gencr(instr);
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emit(uint16_t(0x8141)); //cmp regb, imm32
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emitByte(0xf8 + (instr.regb % RegistersCount));
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emit(instr.imm32);
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emitByte(0x0f); //near jump
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emitByte(jumpCondition(instr) + 0x10);
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i = wrapInstr(i + (instr.imm8 & 127) + 2);
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if (i < instructionOffsets.size()) {
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emit(instructionOffsets[i] - (codePos + 4));
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}
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else {
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callOffsets.push_back(CallOffset(codePos, i));
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codePos += 4;
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}
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}
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void JitCompilerX86::h_CALL(Instruction& instr, int i) {
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void JitCompilerX86::h_CALL(Instruction& instr, int i) {
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genar(instr);
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genar(instr);
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emit(uint16_t(0x8141)); //cmp regb, imm32
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emit(uint16_t(0x8141)); //cmp regb, imm32
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@ -677,6 +695,7 @@ namespace RandomX {
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INST_HANDLE(FPDIV)
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INST_HANDLE(FPDIV)
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INST_HANDLE(FPSQRT)
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INST_HANDLE(FPSQRT)
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INST_HANDLE(FPROUND)
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INST_HANDLE(FPROUND)
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INST_HANDLE(JUMP)
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INST_HANDLE(CALL)
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INST_HANDLE(CALL)
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INST_HANDLE(RET)
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INST_HANDLE(RET)
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};
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};
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@ -110,6 +110,7 @@ namespace RandomX {
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void h_FPDIV(Instruction&, int);
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void h_FPDIV(Instruction&, int);
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void h_FPSQRT(Instruction&, int);
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void h_FPSQRT(Instruction&, int);
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void h_FPROUND(Instruction&, int);
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void h_FPROUND(Instruction&, int);
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void h_JUMP(Instruction&, int);
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void h_CALL(Instruction&, int);
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void h_CALL(Instruction&, int);
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void h_RET(Instruction&, int);
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void h_RET(Instruction&, int);
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};
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};
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@ -19,9 +19,9 @@ along with RandomX. If not, see<http://www.gnu.org/licenses/>.
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#pragma once
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#pragma once
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#define WT_ADD_64 11
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#define WT_ADD_64 15
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#define WT_ADD_32 2
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#define WT_ADD_32 2
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#define WT_SUB_64 11
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#define WT_SUB_64 15
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#define WT_SUB_32 2
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#define WT_SUB_32 2
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#define WT_MUL_64 23
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#define WT_MUL_64 23
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#define WT_MULH_64 10
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#define WT_MULH_64 10
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@ -47,8 +47,9 @@ along with RandomX. If not, see<http://www.gnu.org/licenses/>.
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#define WT_FPDIV 8
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#define WT_FPDIV 8
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#define WT_FPSQRT 6
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#define WT_FPSQRT 6
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#define WT_FPROUND 2
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#define WT_FPROUND 2
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#define WT_CALL 20
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#define WT_JUMP 11
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#define WT_RET 22
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#define WT_CALL 11
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#define WT_RET 12
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constexpr int wtSum = WT_ADD_64 + WT_ADD_32 + WT_SUB_64 + WT_SUB_32 + \
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constexpr int wtSum = WT_ADD_64 + WT_ADD_32 + WT_SUB_64 + WT_SUB_32 + \
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@ -56,7 +57,7 @@ WT_MUL_64 + WT_MULH_64 + WT_MUL_32 + WT_IMUL_32 + WT_IMULH_64 + \
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WT_DIV_64 + WT_IDIV_64 + WT_AND_64 + WT_AND_32 + WT_OR_64 + \
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WT_DIV_64 + WT_IDIV_64 + WT_AND_64 + WT_AND_32 + WT_OR_64 + \
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WT_OR_32 + WT_XOR_64 + WT_XOR_32 + WT_SHL_64 + WT_SHR_64 + \
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WT_OR_32 + WT_XOR_64 + WT_XOR_32 + WT_SHL_64 + WT_SHR_64 + \
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WT_SAR_64 + WT_ROL_64 + WT_ROR_64 + WT_FPADD + WT_FPSUB + WT_FPMUL \
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WT_SAR_64 + WT_ROL_64 + WT_ROR_64 + WT_FPADD + WT_FPSUB + WT_FPMUL \
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+ WT_FPDIV + WT_FPSQRT + WT_FPROUND + WT_CALL + WT_RET;
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+ WT_FPDIV + WT_FPSQRT + WT_FPROUND + WT_JUMP + WT_CALL + WT_RET;
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static_assert(wtSum == 256,
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static_assert(wtSum == 256,
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"Sum of instruction weights must be 256");
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"Sum of instruction weights must be 256");
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2264
src/program.inc
2264
src/program.inc
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