JUMP instruction

This commit is contained in:
tevador 2019-01-11 09:58:06 +01:00
parent 6941b2cb69
commit 557241cd95
7 changed files with 1092 additions and 1214 deletions

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@ -496,6 +496,14 @@ namespace RandomX {
} }
} }
void AssemblyGeneratorX86::h_JUMP(Instruction& instr, int i) {
genar(instr, i);
gencr(instr);
asmCode << "\tcmp " << regR32[instr.regb % RegistersCount] << ", " << instr.imm32 << std::endl;
asmCode << "\t" << jumpCondition(instr);
asmCode << " rx_i_" << wrapInstr(i + (instr.imm8 & 127) + 2) << std::endl;
}
void AssemblyGeneratorX86::h_CALL(Instruction& instr, int i) { void AssemblyGeneratorX86::h_CALL(Instruction& instr, int i) {
genar(instr, i); genar(instr, i);
asmCode << "\tcmp " << regR32[instr.regb % RegistersCount] << ", " << instr.imm32 << std::endl; asmCode << "\tcmp " << regR32[instr.regb % RegistersCount] << ", " << instr.imm32 << std::endl;
@ -554,6 +562,7 @@ namespace RandomX {
INST_HANDLE(FPDIV) INST_HANDLE(FPDIV)
INST_HANDLE(FPSQRT) INST_HANDLE(FPSQRT)
INST_HANDLE(FPROUND) INST_HANDLE(FPROUND)
INST_HANDLE(JUMP)
INST_HANDLE(CALL) INST_HANDLE(CALL)
INST_HANDLE(RET) INST_HANDLE(RET)
}; };

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@ -77,6 +77,7 @@ namespace RandomX {
void h_FPDIV(Instruction&, int); void h_FPDIV(Instruction&, int);
void h_FPSQRT(Instruction&, int); void h_FPSQRT(Instruction&, int);
void h_FPROUND(Instruction&, int); void h_FPROUND(Instruction&, int);
void h_JUMP(Instruction&, int);
void h_CALL(Instruction&, int); void h_CALL(Instruction&, int);
void h_RET(Instruction&, int); void h_RET(Instruction&, int);
}; };

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@ -63,6 +63,7 @@ namespace RandomX {
INST_NAME(FPDIV) INST_NAME(FPDIV)
INST_NAME(FPSQRT) INST_NAME(FPSQRT)
INST_NAME(FPROUND) INST_NAME(FPROUND)
INST_NAME(JUMP)
INST_NAME(CALL) INST_NAME(CALL)
INST_NAME(RET) INST_NAME(RET)
}; };

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@ -603,6 +603,24 @@ namespace RandomX {
} }
} }
void JitCompilerX86::h_JUMP(Instruction& instr, int i) {
genar(instr);
gencr(instr);
emit(uint16_t(0x8141)); //cmp regb, imm32
emitByte(0xf8 + (instr.regb % RegistersCount));
emit(instr.imm32);
emitByte(0x0f); //near jump
emitByte(jumpCondition(instr) + 0x10);
i = wrapInstr(i + (instr.imm8 & 127) + 2);
if (i < instructionOffsets.size()) {
emit(instructionOffsets[i] - (codePos + 4));
}
else {
callOffsets.push_back(CallOffset(codePos, i));
codePos += 4;
}
}
void JitCompilerX86::h_CALL(Instruction& instr, int i) { void JitCompilerX86::h_CALL(Instruction& instr, int i) {
genar(instr); genar(instr);
emit(uint16_t(0x8141)); //cmp regb, imm32 emit(uint16_t(0x8141)); //cmp regb, imm32
@ -677,6 +695,7 @@ namespace RandomX {
INST_HANDLE(FPDIV) INST_HANDLE(FPDIV)
INST_HANDLE(FPSQRT) INST_HANDLE(FPSQRT)
INST_HANDLE(FPROUND) INST_HANDLE(FPROUND)
INST_HANDLE(JUMP)
INST_HANDLE(CALL) INST_HANDLE(CALL)
INST_HANDLE(RET) INST_HANDLE(RET)
}; };

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@ -110,6 +110,7 @@ namespace RandomX {
void h_FPDIV(Instruction&, int); void h_FPDIV(Instruction&, int);
void h_FPSQRT(Instruction&, int); void h_FPSQRT(Instruction&, int);
void h_FPROUND(Instruction&, int); void h_FPROUND(Instruction&, int);
void h_JUMP(Instruction&, int);
void h_CALL(Instruction&, int); void h_CALL(Instruction&, int);
void h_RET(Instruction&, int); void h_RET(Instruction&, int);
}; };

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@ -19,9 +19,9 @@ along with RandomX. If not, see<http://www.gnu.org/licenses/>.
#pragma once #pragma once
#define WT_ADD_64 11 #define WT_ADD_64 15
#define WT_ADD_32 2 #define WT_ADD_32 2
#define WT_SUB_64 11 #define WT_SUB_64 15
#define WT_SUB_32 2 #define WT_SUB_32 2
#define WT_MUL_64 23 #define WT_MUL_64 23
#define WT_MULH_64 10 #define WT_MULH_64 10
@ -47,8 +47,9 @@ along with RandomX. If not, see<http://www.gnu.org/licenses/>.
#define WT_FPDIV 8 #define WT_FPDIV 8
#define WT_FPSQRT 6 #define WT_FPSQRT 6
#define WT_FPROUND 2 #define WT_FPROUND 2
#define WT_CALL 20 #define WT_JUMP 11
#define WT_RET 22 #define WT_CALL 11
#define WT_RET 12
constexpr int wtSum = WT_ADD_64 + WT_ADD_32 + WT_SUB_64 + WT_SUB_32 + \ constexpr int wtSum = WT_ADD_64 + WT_ADD_32 + WT_SUB_64 + WT_SUB_32 + \
@ -56,7 +57,7 @@ WT_MUL_64 + WT_MULH_64 + WT_MUL_32 + WT_IMUL_32 + WT_IMULH_64 + \
WT_DIV_64 + WT_IDIV_64 + WT_AND_64 + WT_AND_32 + WT_OR_64 + \ WT_DIV_64 + WT_IDIV_64 + WT_AND_64 + WT_AND_32 + WT_OR_64 + \
WT_OR_32 + WT_XOR_64 + WT_XOR_32 + WT_SHL_64 + WT_SHR_64 + \ WT_OR_32 + WT_XOR_64 + WT_XOR_32 + WT_SHL_64 + WT_SHR_64 + \
WT_SAR_64 + WT_ROL_64 + WT_ROR_64 + WT_FPADD + WT_FPSUB + WT_FPMUL \ WT_SAR_64 + WT_ROL_64 + WT_ROR_64 + WT_FPADD + WT_FPSUB + WT_FPMUL \
+ WT_FPDIV + WT_FPSQRT + WT_FPROUND + WT_CALL + WT_RET; + WT_FPDIV + WT_FPSQRT + WT_FPROUND + WT_JUMP + WT_CALL + WT_RET;
static_assert(wtSum == 256, static_assert(wtSum == 256,
"Sum of instruction weights must be 256"); "Sum of instruction weights must be 256");

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