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Render imm32 as signed in RandomX code

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This commit is contained in:
tevador 2019-02-09 16:19:15 +01:00
parent 9af0cbf108
commit 2798d78717
6 changed files with 706 additions and 706 deletions
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1
src/AssemblyGeneratorX86.cpp
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@ -20,7 +20,6 @@ along with RandomX. If not, see<http://www.gnu.org/licenses/>.
#define MAGIC_DIVISION
#include "AssemblyGeneratorX86.hpp"
#include "common.hpp"
#include "instructions.hpp"
#ifdef MAGIC_DIVISION
#include "divideByConstantCodegen.h"
#endif

1
src/CompiledVirtualMachine.cpp
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@ -19,7 +19,6 @@ along with RandomX. If not, see<http://www.gnu.org/licenses/>.
#include "CompiledVirtualMachine.hpp"
#include "common.hpp"
#include "instructions.hpp"
#include <stdexcept>
namespace RandomX {

20
src/Instruction.cpp
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@ -45,7 +45,7 @@ namespace RandomX {
os << "r" << (int)dst << ", r" << (int)src << std::endl;
}
else {
os << "r" << (int)dst << ", " << imm32 << std::endl;
os << "r" << (int)dst << ", " << (int32_t)imm32 << std::endl;
}
}
@ -63,7 +63,7 @@ namespace RandomX {
}
void Instruction::h_IADD_RC(std::ostream& os) const {
os << "r" << (int)dst << ", r" << (int)src << ", " << imm32 << std::endl;
os << "r" << (int)dst << ", r" << (int)src << ", " << (int32_t)imm32 << std::endl;
}
//1 uOP
@ -72,7 +72,7 @@ namespace RandomX {
os << "r" << (int)dst << ", r" << (int)src << std::endl;
}
else {
os << "r" << (int)dst << ", " << imm32 << std::endl;
os << "r" << (int)dst << ", " << (int32_t)imm32 << std::endl;
}
}
@ -90,7 +90,7 @@ namespace RandomX {
}
void Instruction::h_IMUL_9C(std::ostream& os) const {
os << "r" << (int)dst << ", " << imm32 << std::endl;
os << "r" << (int)dst << ", " << (int32_t)imm32 << std::endl;
}
void Instruction::h_IMUL_R(std::ostream& os) const {
@ -98,7 +98,7 @@ namespace RandomX {
os << "r" << (int)dst << ", r" << (int)src << std::endl;
}
else {
os << "r" << (int)dst << ", " << imm32 << std::endl;
os << "r" << (int)dst << ", " << (int32_t)imm32 << std::endl;
}
}
@ -158,7 +158,7 @@ namespace RandomX {
os << "r" << (int)dst << ", r" << (int)src << std::endl;
}
else {
os << "r" << (int)dst << ", " << imm32 << std::endl;
os << "r" << (int)dst << ", " << (int32_t)imm32 << std::endl;
}
}
@ -194,11 +194,11 @@ namespace RandomX {
}
void Instruction::h_IDIV_C(std::ostream& os) const {
os << "r" << (int)dst << ", " << (uint32_t)imm32 << std::endl;
os << "r" << (int)dst << ", " << imm32 << std::endl;
}
void Instruction::h_ISDIV_C(std::ostream& os) const {
os << "r" << (int)dst << ", " << imm32 << std::endl;
os << "r" << (int)dst << ", " << (int32_t)imm32 << std::endl;
}
void Instruction::h_ISWAP_R(std::ostream& os) const {
@ -300,13 +300,13 @@ namespace RandomX {
}
void Instruction::h_COND_R(std::ostream& os) const {
os << "r" << (int)dst << ", " << condition((mod >> 2) & 7) << "(r" << (int)src << ", " << imm32 << ")" << std::endl;
os << "r" << (int)dst << ", " << condition((mod >> 2) & 7) << "(r" << (int)src << ", " << (int32_t)imm32 << ")" << std::endl;
}
void Instruction::h_COND_M(std::ostream& os) const {
os << "r" << (int)dst << ", " << condition((mod >> 2) & 7) << "(";
genAddressReg(os);
os << ", " << imm32 << ")" << std::endl;
os << ", " << (int32_t)imm32 << ")" << std::endl;
}
void Instruction::h_ISTORE(std::ostream& os) const {

1
src/InterpretedVirtualMachine.cpp
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@ -19,7 +19,6 @@ along with RandomX. If not, see<http://www.gnu.org/licenses/>.
//#define TRACE
//#define FPUCHECK
#include "InterpretedVirtualMachine.hpp"
#include "instructions.hpp"
#include "dataset.hpp"
#include "Cache.hpp"
#include "LightClientAsyncWorker.hpp"

1
src/main.cpp
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@ -29,7 +29,6 @@ along with RandomX. If not, see<http://www.gnu.org/licenses/>.
#include <cstring>
#include "Program.hpp"
#include <string>
#include "instructions.hpp"
#include <thread>
#include <atomic>
#include "dataset.hpp"

1388
src/program.inc
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